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NAVAL POSTGRADUATE SCHOOL
Monterey, California
THESIS
A DIGITALLY TUNED AM/FM
RADIO
by
Dogan Ozdemir
and
Nurettin Bal
December 1980
Thesis Advisor:
G. A. Mvers
Approved for public release; distribution unlimited.
T197807
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REPORT DOCUMENTATION PAGE
READ INSTRUCTIONS
BEFORE COMPLETniG FORM
\. ntPOBT numsca
2. GOVT ACCESSION NO.
3. RECIPIENT’S CATALOG NUMBER
4. title Can^ 5u4«rr«)
A Digitally Tuned AM/FM Radio
5. TYPE OF REPORT k PERIOD COVERED
Master's Thesis;
December 1980
«. PCAFOAMING OAG. REPORT NUMBER
7. AUTMOnro
Dogan Ozdemir
Nurettin Bal
a. contract or grant NUMSERr*)
• . PEMrOMUINC OMOANIZATION NAME AND AOONCSS
Naval Postgraduate School
Monterey, California 93940
10. PROGRAM ELEMENT. PROJECT. TASK
AREA k PORK UNIT NUMBERS
II. contnollinc omcc name and aooncss
Naval Postgraduate School
Monterey, California 93940
IZ. AEPOMT OATS
December 1980
IS. number OF pages
86
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IS. security class. (oI mu riport)
Unclassified
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SCHEDULE
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Approved for public release; distribution unlimited.
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Frequency Synthesizer
Phase-Locked Loop (PLL)
Electronic Prograrating
Voltage Controlled Oscillator (VCO)
20. asst A ACT fCanf/m*# on rovoroo oldm if noeooo^fT by kiock numk^)
This report describes the design and operation of a
relatively economical, single crystal, frequency synthesizer
that generates the required local oscillator frequencies for
commercial AM and FM broadcast receivers. Selection of a
desired station is accomplished by electronic programming
using pushbutton control. Fine tuning is not necessary.
Receiver frequency drift is not significant because the local
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(20. ABSTRACT Continued)
oscillator frequency is crystal controlled. Low-cost medium-
scale integrated circuits and a large-scale integrated
circuit (LSI) are the building blocks of this synthesizer.
Frequency synthesis techniques, elements of the system
design and experimental results are also presented.
UNCLASSIFIED
KCUMtTV eUAMI^lCATIOM 0^ TnI*
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Approved for public release; distribution unlimited.
A Digitally Tuned AM/FM Radio
by
Dogan Qzdemir
Lieutenant, Turkish Navy
B.S.E.E., Naval Postgraduate School, 1980
and
Nurettin Bal
Lieutenant, Turkish Navy
B.S.E.E., Naval Postgraduate School, 1980
Submitted in partial fulfillment of the
requirements for the degree of
MASTER OF SCIENCE IN ELECTRICAL ENGINEERING
from the
NAVAL POSTGRADUATE SCHOOL
December 1980
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ABSTRACT
This report describes the design and operation of a
relatively economical, single crystal, frequency synthesizer
that generates the required local oscillator frequencies for
commercial AM and FM broadcast receivers. Selection of a
desired station is accomplished by electronic programming
using pushbutton control. Fine tuning is not necessary.
Receiver frequency drift is not significant because the
local oscillator frequency is crystal controlled. Low-cost
medium-scale integrated circuits and a large-scale
integrated circuit (LSI) are the building blocks of this
synthesizer.
Frequency synthesis techniques, elements of the system
design and experimental results are also presented.
4
TABLE OF CONTENTS
I. INTRODUCTION 12
A. OBJECTIVE 12
B. BACKGROUND 12
C. SUMMARY OF THE RESULTS 14
II. FREQUENCY SYNTHESIS 16
A, FREQUENCY SYNTHESIS TECHNIQUES 16
1. Incoherent Synthesis 16
2. Coherent Direct Synthesis 16
3 . Coherent Indirect Synthesis 17
a. Analog phase-locked loop
synthesis 18
b. Digital phase-locked loop
synthesis 18
3. AM/FM RADIO FREQUENCY SYNTHESIZER
REQUIREMENTS 21
III. SYSTEM DESIGN 23
A. CONSIDERATIONS LEADING TO A BLOCK
DIAGRAM 23
1. Reference Frequency 23
2. Phase Detector 25
3. Voltage Controlled Oscillator 25
4. Lowpass Filter 26
5. Programmable Divider 27
B. SUBSYSTEM DESIGN 29
1. Voltage Controlled Oscillator (VCO) - 29
5
a
AM VCO
30
b. FM VCO
2. Reference Oscillator, Phase
Detector, Programmable Divider
3. Prescaler
4. Lowpass Filter
5. Station Programming Circuit
a. Selection Switches
b. Switch Debouncing
c. Encoder
d. Shift Register and NAND Gate —
e. Latches
f. Programmable Read Only
Memory (PROM)
g. BCD/7-Segment Decoder/Drivers
and Displays
IV. SUMMARY OF OPERATION AND PERFORMANCE
CHARACTERISTICS
A. SYSTEM OPERATION
3. EXPERIMENTAL RESULTS
V. CONCLUSIONS
APPENDIX A; DESIGN THEORY
LIST OF REFERENCES
BIBLIOGRAPHY
INITIAL DISTRIBUTION LIST
35
38
43
43
47
47
47
48
48
50
50
53
55
55
64
75
78
84
85
86
6
LIST OF FIGURES
Figure No.
1. Analog Phase-Locked Loop Synthesis 19
2. Digital Phase-Locked Loop Synthesis 20
3. Evolution of the Digital AM/FM Frequency
Synthesizer 24
4. Schematic Diagram of the AM VCO 31
5. The Transfer Characteristics of the AM VCO - 32
6. Diode Capacitance versus Reverse Voltage 33
7. Schematic Diagram of the FM VCO 36
8. The Transfer Characteristics of the FM VCO - 37
9. VCO Internal Noise 39
10. Loop Response to the VCO Noise 39
11. Block Diagram of the MM 55110 40
12. Voltage-Phase Characteristic of the Phase
Detector 42
13. Divide-by-20 Prescaler Circuit 42
14 . Normalized Transient Response of the Phase-
Lag-Lead Filter 45
15. Switch Debouncing Circuitry 49
16. Timing Circuitry 49
17. Timing Diagram for Circuitry of Fig. 16 51
18. The Encoder and Latch Circuitry 52
19. PROM Circuitry 54
20 . Complete Block Diagram of the PLL
Frequency Synthesizer 56
7
21. Schematic Diagram of the Synthesizer
22. Schematic Diagram of the Programming
Circuit
23. Schematic Diagram of the Display Circuit
24. Output of the Phase Detector at Lock
25. Output of the AM VCO
26. Output of the FM VCO
27. Output of the MC 12012 shown in Fig. 13
28. Output of the MC 3060 shown in Fig. 13
29. Spectrum of the AM VCO Output
30. Spectrum of the FM VCO Output
31. The Breadboard System of the Synthesizer
A1 . Basic Block Diagram of the Phase-Locked
Loop
A2. Phase-Lag-Lead Lowpass Filter
57
58
59
61
62
63
65
65
72
73
76
79
80
8
LIST OF SYMBOLS
IN
f ^
out
^ref
Af
AGO
AM
BCD
T
CMOS
ECL
FM
Hex
IC
IF
^0
L
LO
LPF
LSI
M
Programmable divider input frequency
Synthesizer output frequency
Reference frequency
Total frequency variation
Settling time
Automatic gain control
Amplitude modulation
Binary coded decimal
Input capacitance of the MC 1648
Variable capacitance of the varactor diode
Complementary metal-oxide semiconductor
Emitter coupled logic
Frequency modulation
Hexadecimal
Integrated circuit
Intermediate frequency
Gain constant of the phase detector
Gain constant of the VCO
Reference frequency division ratio
Local oscillator
Lowpass filter
Large-scale integrated circuit
Variable modulus of the programmable counter
9
MSB
N
P
PD
PLL
RF
PROM
TTL
^2
vco
c
^e(t)
Most significant bit
Total division ratio
Modulus of prescaler
Phase detector
Phase-Locked loop
Radio frequency
Programmable read only memory
Transistor to transistor logic
Filter coefficient of the lowpass filter
Filter coefficient of the lowpass filter
Voltage controlled oscillator
Damping ratio
Input frequency to the PLL
Natural frequency
Output frequency of the PLL
Input phase angle to the PLL
Error phase angle of the PLL
Output phase angle of the PLL
10
ACKNOWLEDGEMENT
The authors wish to express their sincere appreciation
to Professor Glen A. Myers for his guidance and assistance.
11
I.
INTRODUCTION
A. OBJECTIVE
Of interest is the design and construction of a frequency
synthesizer for a commercial AM/FM radio, which uses inte-
grated circuits to minimize size and cost and which provides
the user with precise and versatile electronic programming
of the desired station's frequency.
B . BACKGROUND
In conventional AM/FM radio receivers, it is necessary
to turn a knob for station or channel tuning. This
electromechanical system generates the appropriate frequency
of a local oscillator by means of an inductance-capacitance
oscillator. The problems involved in "knob- tuning" are;
1. Accurate tuning depends on the user's hearing
capability .
2. The output of a continuously tunable local oscillator
(LO) is subject to frequency drift which means occasional
retuning may be necessary.
Stable, rapid and accurate frequency selection is
available today using frequency synthesizers. In general,
all devices generating frequencies which are rational
multiples (or nearly rational multiples , in the case of
interpolation, etc.) of a' standard input frequency are
12
-rtjjg.l* ■ .' -.-
called frequency synthesizers, irrespective of the actual
frequency changing process involved.
The frequency synthesizer is a tunable oscillator
having exceptional qualities such as:
1. Long-term stability equal to that of one or a few
reference signals (which can be very stable) .
2. Perfect resettability .
3. An extremely large frequency range (decade
synthesizers) .
4. Incremental tuning independent of the value of the
output frequency.
Frequency synthesizers, therefore, function as oscil-
lators and in many respects perform better than continuously
tuned oscillators. An outstanding advantage of frequency
synthesizers, in these times of automation, is their
adaptability to remote and digital tuning and compatibility
with computer control.
Because they are able to generate a large number of
frequencies in a broad frequency band with considerable
precision, frequency synthesizers are used in many
measuring applications (frequency comparison, phase
measurement, etc.). And they form an indispensable part
of the instrumentation in standard frequency and time
laboratories .
In ‘radio communications, the use of frequency synthe-
sizers in transmitters is a well established technique.
13
I
The introduction of digital synthesizers and integrated
circuit (IC) technology in the mid-1960’s paved the way
for their widespread use in receivers. With the present
state of the art, use of a coininunications system in which
all the carrier and heterodyning frequencies used in the
transmitter and receiver are derived from primary (atomic)
standard is conceivable.
Today, many commercial television receivers have
pushbutton tuning which is possible through use of a
frequency synthesizer.
C. SUMMARY OF THE RESULTS
A frequency synthesizer having the following charac-
teristics was designed, built and tested.
(1) Tuning range: 955 kHz to 2055 kHz for AM
77.4 MHz to 97.2 MHz for FM
(2) Electronic tunable in 10 kHz steps (111 channels)
for AM and 200 kHz steps (100 channels) for FM.
(3) Frequency stability of + 30 Hz or 0.0042% for AM
and of + 400 Hz or 0.00082% for FM.
(4) Spurious outputs better than -30 db for AM and
-48 db for FM.
(5) Estimated volume of final package that contains
five LSI's is 75 cm^ .
(6) Estimated cost of the synthesizer in mass production
is $30.
14
Results of this research clearly show that a PLL, in
conjunction with a programmable divider, can be used as a
frequency synthesizer and maintain frequency stability.
15
II. FREQUENCY SYNTHESIS
A. FREQUENCY SYNTHESIS TECHNIQUES
Frequency synthesis techniques can be identified as
either
1. Incoherent synthesis
2. Coherent direct synthesis
3. Coherent indirect synthesis
1 . Incoherent Synthesis
Incoherent synthesis utilizes essentially the
method of successive heterodyning. The exact manner in
which output frequencies are generated from input fre-
quencies in incoherent synthesis varies depending on the
application. Output frequency range, value of the smallest
frequency increment, frequency stability and accuracy,
level of the spurious outputs, size, cost and power
consximption are factors governing the choice of design.
The main goal of this technique, though, remains the same
in all cases — to minimize the number of crystal and basic
building blocks such as oscillators, mixers, and filters.
2 . Coherent Direct Synthesis
The main difference between incoherent and coherent
synthesis is the number of frequency sources utilized in
the process of frequency generation. In the incoherent
synthesis approach there are numerous crystal-controlled
16
oscillators; in the coherent direct synthesis approach,
only one reference source is used. Hence, the stability
and accuracy of the output frequency in this method are
the same as the stability and accuracy of the reference
source . This feature makes coherent direct synthesis
attractive.
3 . Coherent Indirect Synthesis
Coherent indirect synthesis utilizes the principle
of feedback to generate frequencies in increments. The
technique, known as phase-locking, differs from coherent
direct synthesis in many respects. The system analysis
of coherent indirect synthesis centers on an investigation
of phase-locked loop (PLL) stability and acquisition.
.Mixers, multipliers, dividers, and filters are used in
synthesis, but so also are voltage-controlled oscillators
(VCO's), programmable dividers, phase detectors and
frequency discriminators. The main problem associated
with coherent indirect synthesis techniques is dynamics
of the feedback network (loop stability and acquisition) .
By providing small-size, light-weight equipment that
consumes little power, these techniques exhibit many
advantages not offered by coherent direct synthesis.
Coherent indirect synthesis techniques can be grouped as:
a. Analog phase-locked loop synthesis
b. Digital phase-locked loop synthesis
17
a. Analog phase-locked loop synthesis
Fig. 1 is a block diagram of an analog PLL
^2
frequency synthesizer where the expression I
m=x.
describes an input signal with a high harmonic Content .
The harmonics of the signal that are passed by the filter
one at a time are through ^2^ref* rest of the
harmonics suppressed by the filter are denoted as R. The
frequency of the VCO, ^out' downconverted and compared
to the reference frequency, When the difference
between these two frequencies is small, the phase detector
generates a slowly varying AC voltage, which is passed by
the lowpass filter, and pulls the VCO into lock. Under
locked condition, the output of the phase detector is a
DC voltage whose amplitude and polarity are determined by
the amount and direction of phase displacement between the
reference and downconverted VCO signals. The lowpass
filter (often a combination of a lowpass filter and lag-
lead network) changes the amplitude and phase of individual
signals passing through it as a function of the working
frequency to achieve stable loop performance.
b. Digital phase-locked loop synthesis
A technique which is of considerable current
interest is the digital phase-locked loop synthesis. The
basic form of a digital PLL is shown in Fig. 2. The loop
consists of a VCO, variable-ratio frequency divider, phase
comparator, and lowpass filter. The VCO output is divided
18
GENERATOR
04 r
X X
II II
C2 S
19
Fig. 1. ANALOG PHASE-LOCKED LOOP SYNTHESIS
DETECTOR
<D
•z
II
4J
3
0
U
o
o
>
20
Fig. 2. DIGITAL PHASE-LOCKED LOOP SYNTHESIS
and compared with a stable reference. Error voltages
derived from the phase comparator maintain the VCO on
frequency. Frequency selection is accomplished by a
channel selector (the control panel) , which varies the
division ratio of the frequency divider. For locking to
occur,
f
out
N
■ref
( 2 . 1 )
where N is an integer.
Eq. (2.1) indicates that the smallest frequency
increment generated by the loop is equal to the reference
frequency, The important characteristics offered
by a digital PLL are small size and low DC power consump-
tion. At low frequencies, when slow-speed integrated
circuits are used, DC power drain is very small, making
the digital synthesizer suitable for battery operation.
B. AM/FM RADIO FREQUENCY SYNTHESIZER REQUIREMENTS
The synthesizer of interest must generate the required
local oscillator frequencies for AM and FM broadcast bands
which are about 88 MHz apart.
The AM broadcast band consists of channels 10 kHz wide
starting at 500 kHz. Therefore, the carrier for the first
channel is at 500 kHz, and the carrier for the last channel
is at 1600 kHz. The- receiver local oscillator must
generate frequencies separated by 455 kHz from the broadcast
21
frequencies to accommodate the receiver intermediate
frequency (IF) amplifier. Therefore, the local oscillator
frequencies required are 955 kHz to 2055 kHz with 10 kHz
channel spacing. A list of all the required frequencies
for all the stations in the AM broadcast band is a part
of Table I in section IV. A.
The FM broadcast band occupies 20 MHz between 88 MHz
and 108 MHz. There are 100 channels which are spaced
200 kHz apart. The carrier for the first channel is at
88.1 MHz and the last carrier for the last channel is
107.9 MHz. Again, to keep the IF frequency at 10.7 MHz,
the local oscillator frequency should be 10.7 MHz from
the carrier frequency. If the lower band is chosen, the
local oscillator frequencies required are 77.4 MHz to
97.2 MHz with 200 kHz channel spacing. A list of all the
required frequencies for all the stations in the FM
broadcast band is a part of Table II in section IV. A.
22
III. SYSTEM DESIGN
A. CONSIDERATIONS LEADING TO A BLOCK DIAGRAM
It is first necessary to choose the proper technique
for the desired frequency synthesizer among the frequency
synthesis techniques mentioned in Chapter I. Initially,
the techniques which utilize a single reference source were
considered, in order to rely on the stability and accuracy
of a single crystal oscillator. Between the choices of
direct synthesis and coherent indirect synthesis, both of
which met initial requirement, the latter was chosen because
of its advantages such as phase noise, switching speed, fre-
quency increments, small size and light weight [Ref. 1].
Once the PLL technique is chosen, the question of having
a single loop for both AM and FM bands arises. In that case,
every part of the PLL loop shown in Fig. 3 is to function
in the same way for AM and FM, under the constraint of
operating in two different frequency bands which are about
88 MHz apart. The problems associated with the frequency
requirement are discussed in the following paragraphs for
all the parts of the loop.
1 . Reference Frequency
As pointed out in section II.A.3.b of this report,
in order for locking to occur.
f
out
N
’ref
( 2 . 1 )
23
(a)
(b)
Fig. 3. EVOLUTION OF THE DIGITAL AM/FM FREQUENCY SYNTHESIZER
24
which means that frequencies may be generated which are
integer multiples of the reference frequency. Hence, the
same reference frequency should be able to generate the
AM and FM local oscillator frequencies. A 5 kHz frequency
is the largest possible reference which will generate the
AM local oscillator frequencies from 955 kHz to 2055 kHz
with 10 kHz channel spacing and the FM local oscillator
frequencies from 77.4 MHz to 97.2 MHz with 200 kHz channel
spacing. This is so because 5 kHz is the least common integer
factor of 955 kHz, 965 kHz ... 2055 kHz.
2 . Phase Detector
Phase comparison is accomplished at a reference
frequency There are many reasons for making the phase
detector frequency as large as possible. Phase noise,
switching time, and spurious frequency modulation (FM) at
f^g^ are among the most important considerations [Ref. 1] .
Group loop currents, which present a problem below approxi-
mately 5 kHz, are another reason for making large.
In the design of this particular synthesizer, the
largest possible reference frequency of 100 kHz for FM was
lowered to the largest reference frequency of 5 kHz for AM
to utilize the same phase detector as shown in Fig. 3b.
3 . Voltage Controlled Oscillator (VCO)
The most severe constraint on the single loop AM/
FM frequency synthesizer is the VCO due to its tuning range
and linearity. If a single VCO were to be used in the loop,
it would require linear operation over a 100 MHz tuning
25
range. Such a VCO would have a conversion gain of 10^ Hz/volt
where
K
0
Conversion Gain = ^and in the linear region
Oontrol voltage range that provides
the linear operation
100 MHz
10 V (Assumed)
10^ Hz/volt
This means that the control voltage step required between
any two adjacent channels in AT4 would be 10 voltes which
is very difficult to control. There are two ways to have
different tuning ranges for each broadcast band — by elec-
tronic switching of the elements of the VCO or by using two
separate VCO's. It was decided to use two VCO ' s because
of circuit simplicity and reliability of operation. The
synthesizer involving two VCO's is shown in Fig. 3b.
4 . Lowpass Filter
The transient performance and the frequency response
of the PLL is dependent upon the phase detector conversion
gain K^, the VCO conversion gain Kq and the choice of the
filter [Ref. 2]. As shown in Fig. 3b, there is one phase
detector and there are two VCO's with different conversion
gains (AM) , Kq(FM) . What happens in the performance of
the loop with two separate ' s is that one of the two
calc\ilations using each Kq gives poorer performance for the
loop. The Kq which causes that performance is taken into
account in determining the elements of the loop filter which
are considered in section 3.4 of this chapter.
26
5 . Programmable Divider
The required division ratios, to achieve the AM and
FM local oscillator frequencies using a 5 kHz reference
frequency, are given below:
AM: Local oscillator frequencies = 955 kHz to 2055 kHz
Division ratios = 191 to 411
FM: Local oscillator frequencies = 77.4 MHz to 97.2 MHz
Division ratios = 15,480 tO 19,940
The maximum division ratio is less than 2^^. Using four
four-bit programmable dividers, division by any integer up
to 2^^ is possible. Hence, the desired division ratios are
easy to implement, providing programmable frequency dividers
are available at frequencies up to 100 MHz. Since this is
not the case, then for FM it is necessary to down convert
the signal between the FM VCO and programmable dividers.
The approach to down conversion used here is prescaling of
the FM VCO output frequency by a fixed high speed divider
until the programmable divider range is reached. In this
project, frequency division by P = 20 is used to keep the
200 kHz channel spacing compatible with the 10 kHz AM channel
spacing. The block diagram of the synthesizer design at this
point is shown in Fig. 3c.
6 . Construction and Operation
The required reference frequency is 5 kHz. Since
the crystal oscillator design is somewhat difficult and
expensive at low frequencies, a high frequency crystal
27
(c)
(d)
Fig. 3. EVOLUTION OF THE DIGITAL AM/FM FREQUENCY SYNTHESIZER
28
oscillator followed by a divider circuit should be used.
In order to generate the reference signal to be used in
the phase detector, the output of the crystal oscillator
is divided by L.
The next step in the design of the PLL is selection
of the specific IC's. After all of the available PLL inte-
grated circuits were taken into consideration, only a large-
scale integrated circuit (LSI) , which contained a reference
oscillator, a reference frequency divider, a phase detector,
and a programmable divider, was chosen because of its rela-
tively small size and low cost.
The design of the electronic programming part of
the system is a straightforward digital process whereby a
column of channel selection switches set by the operator
controls the programmable divider.
Design and circuit of each part of the system are
given in the next section.
B. SUBSYSTEM DESIGN
In this section the design and performance of the sub-
systems of the digitally tuned AM/FM radio synthesizer of
Fig. 3d are presented.
1. Voltage Controlled Oscillator (VCO)
The MC 1648 is an emitter-coupled oscillator, con-
structed on a single monolithic silicon chip. The oscillator
requires an external parallel tank circuit consisting of
an inductor (L) and capacitor (C) .
29
A varactor diode. Motorola MV 1404, is incorporated
into the tank circuit to provide a voltage variable input
for the oscillator. The connection of the varactor diode
and other circuitry external to the MC 1648 differs for the
AM VCO and FM VCO .
a . AM VCO
Fig. 4 is the schematic diagram, and Fig. 5 is
the transfer characteristic of the AM VCO. The VCO is in-
tended to operate from 955 kHz to 2055 kHz. The actual
operating range has to be determined by considering the worst
case transition from one frequency to another. In this de-
sign, an acceptable frequency overshoot of 25% was chosen.
This now places the AM frequency band for the LO in the
range 716 kHz to 2568 kHz.
The VCO design in the range of 716 kHz to
2568 kHz starts with the resonant frequency formula [Ref. 3]
f = — (3.1)
2tt/LC
In the VCO circuit of Fig. 4, the value of the
tank circuit capacitance C is Cq + C^ where
Cq = 6 pF, input capacitance of the MC 1648 and
C = the varactor diode capacitance.
T
The value of C^ changes according to the voltage applied.
Fig. 6 shows the variation of C^ with voltage.
30
+ 5V
D : MV 1404 VARACTOR DIODE
L : ADJUSTABLE RF COIL (200uH-400uH)
Fig. 4. SCHEMATIC DIAGRAM OF THE AM VCO
31
2.2
OUTPUT FREQUENCY (MHz )
* • ' ■ I ■ T ■ » ■ I. -■■■ I. I , I . ,
1,5 2.0 2,5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Fig. 5. THE TRANSFER CHARACTERISTIC OF THE AM VCO
32
I
Ct. capacitance (pf)
10 2 ” 3 0 ") 7 '*
Vr REVF'^^F ri tagt
Fig. 6. DIODE CAPACITANCE VERSUS REVERSE VOLTAGE
From Eq. (3.1),
LC
2 2
47T^f^
where;
716 kHz < f < 2568 kHz.
Solution for LC gives
3.841 (mH) (pF) 1 LC < 49.402 (,nH) (pF) .
Picking L = 0.3 mH gives
12.8 (pF) 1 C < 164.6 (pF)
6.8 (pF) 1 1 158.6 (pF)
The limits of the capacitance, C^, correspond to the reverse
bias voltage of the MV 1404 from 1 volt to 7.5 volts which
are found by means of the varactor diode's voltage-capaci-
tance characteristic (Fig. 6) . To obtain a sine wave at
the output, a resistor is added from the AGC circuit (pin 5)
to ground (Fig. 4) .
The conversion gain, K^, which is simply the
slope of the transfer characteristic, can be calculated as
K,
2tt ( f^-f^)
2tt(2-1) xlO
6 - 1.6
= 1,427,998 Rad/volt-sec.
34
■'i-ir*
b. FM VCO
The schematic diagram and the transfer character-
istic of the FM VCO are shown in Fig. 7 and Fig. 8 respectively.
The frequency range is the only difference in
the design of the FM VCO from that of the AM VCO. The LO
frequency range for FM is 58.05 MHz to 121.5 MHz when 25%
overshoot values are included. From Eq. (3.1)
LC
4it
where :
58.05 MHz 1 f <. 121.5 MHz.
Solution for LC gives
I. 716 (yH) (pF) 1 LC < 7.516 (yH) (pF)
Picking L = 0.1 yH gives
17.16 (pF) 1 C < 75.16 (pF)
II. 16 (pF) 1 1 69.16 (pF)
From Fig. 6, it is necessary for the reverse bias voltage of
the varactor diodes to vary from 3.1 volts to 7.5 volts in
order to obtain C^ within the limits given above. To extend
the useful frequency range of the device a 1 kohm resistor
is added to the AGC circuit at pin 5 as in Fig. 7.
35
+ 5V
D : MV 1404 VARACTOR DIODE
L : MICRO METAL TOROIDAL CORE # T30-22
5 TURNS OF NO. 20 COPPER WIRE
Fig. 7. SCHEMATIC DIAGRAM OF THE FM VCO
36
96
94
92
90
38
36
34
82
30
78
OUTPUT FREQUENCY (MHz)
(VOLTS)
5.8 5.9 6.0 6.1 6.2 6.3 6.4 6.5 6.6 6.7
Fig. 8. THE TRANSFER CHARACTERISTIC OF THE FM VCO
37
The conversion gain, , is calculated from
Fig. 8 as:
K
0
2tt (92-82) xio
6.56-6.02
6
116.3x10^ Rad. /volt- sec.
There is a variation of the output frequency
due to internal noise of the MC 1648. The plot of this
variation is given in Fig. 9. The analysis of the frequency
response of the closed loop shows that the noise component
in the VCO above the loop natural frequency, oj^, will pass
unattenuated and those below will have the same degree of
suppression as seen in Fig. 10. Therefore, the VCO internal
noise must be considered when the loop natural frequency is
chosen.
2 . Reference Oscillator, Phase Detector, Programmable
Divider
The PLL frequency synthesizer used in this project
is a monolithic metal gate CMOS integrated circuit identi-
fied as MM 55110. Fig. 11 shows the circuit functions and
pin connections. The device operates from a single power
supply and contains an oscillator with feedback resistor,
divider chian, a binary input programmable divider with con-
trol logic for transmit mode [-|- (M+91) ] or receive mode
[-f-M] and the necessary phase detector logic. (The device
can be used in double IF or single IF systems.)
38
Af FRfcQatKlCY KMS (h/»
1 0 '0 100
f, opeaAxiwo FftjEQuencY, (mht)
Fig. 9. VCO INTERNAL NOISE
1-00 FpeauCNCY
Fig. 10. LOOP RESPONSE TO THE VCO NOISE
39
5.12 10.24
MHZ MHz FI1.TER FILTER <l>VCO
OUT OUT FS IN OUT OUT
Q
a
N N a u:
=: a a u
X M p: X o
X
X
a
40
Fig. 11. BLOCK DIAGRAM OF THE MM 55110
I
The MM 55110 uses a 10.24 MHz quartz crystal to
determine the reference frequency, and it has a selectable
2^^ or 2^^ divider chain which gives either a 10 kHz or
5 kHz reference frequency. The selection of reference fre-
quency is made by use of the FS (Frequency Select) pin.
Signal level at pin 2 in Fig. 11 may be 1 volt peak-
to-peak. An internal amplifier adjusts the input signal
level to that required by the programmable divider circuit.
The divider circuit divides the input frequency by M £ 1023
in the receive mode (M £ 1114 in the transmit mode) . Selec-
tion of M and hence station selection is accomplished by
mechanical switches or by external electronic programming
of the programmable divider which is done in this project
using a PROM (Programmable Read Only Memory) .
Inputs to the programmable divider are binary sig-
nals having a high level above 6 volts . Operational ampli-
fiers were used to amplify the 4.3 volts high level voltage
of the PROM outputs to the 7.5 volts high level voltage of
the programmable divider inputs .
The phase detector output voltage is inversely re-
lated to the frequency of the input signal. This output
has a high impedance state when in the lock mode. The Lock
Detector output (LD) also goes to a high statae under lock
condition. From the phase detector's voltage-phase charac-
teristic shown as Fig. 12, the phase detector conversion
gain K , is calculated as ;
41
Fig. 12. VOLTAGE-PHASE CHARACTERISTIC OF THE PHASE DETECTOR
42
7.19 - 0.29
4tt
0.549 volt/Rad.
K
~ \
4tt
3 . Prescaler
An ECL integrated circuit chip MC 12012 and a TTL
integrated circuit chip MC 3060 (-^ 2 circuit) are used as
a fixed, divide-by-20 prescaler to accomplish the down con-
version of the FM VCO output to the range from 3.87 MHz to
4.68 MHz. The MC 12012 alone could have been used as a
fixed divide-by-10 prescaler, if the practical upper limit
(7 MHz) of the working range of the programmable divider
in the MM 55110 would have been close to its theoretical
limit 10.23 MHz. The prescaler circuit is shown in Fig. 13.
4 . Lowpass Filter
As mentioned in Appendix A, the transfer function
of the loop filter used in this project is
F(S)
ItST^
1 + ST^
(A-3)
The loop transient response, whose psecif ications
are settling time and maximum overshoot, determine the filter
coefficient T^ and T 2 . Reasonable values for the transient
response are assumed to be
Maximum overshoot < 25%
Settling time (t^) = 10 msec
Formulas developed in Appendix A are used to calculate the
filter elements R^^, R 2 and C:
43
^0 ^ N
CNo.2 ■
(A-12)
R = ^ N
2 "
(A-11)
C =
2 ?
N
''2% ^2V0
(A-13)
The values to be used in the above formulas are;
Kq - 1,427,998 Rad/ volt-sec for the AM VCO
g
Kq = 116.3x10 Rad/volt-sec for the FM VCO
= 0.549 Volt/Rad
N = N =411 for the AM loop
max ^
N = N = 19,440 for the FM loop
max '■
C, are obtained from Fig. 14 using the response
specifications .
It is apparent that there are two different sets of
values (Kq,N) to be used in the calculations of the filter
element values which should be the same for both of the loops.
The procedure uses filter element values calculated by
choosing and N values for one loop. Then, these values
are used to determine the transient response (settling time
and maximum overshoot) of the other loop. A result is that
the AM loop provides slower response with higher overshoot
44
Normalized Output Response
Fig. 14. NORMALIZED TRANSIENT RESPONSE OF THE
PHASE-LAG-LEAD FILTER
45
than the FM loop. Therefore, the worst-case design requires
use of the AM VCO conversion gain and maximum division ratio.
From Fig. 14 it is seen that a damping ratio C = 0.8
will produce a peak overshoot less than 25% and will settle
to within 5%atut =4.6 radians. Since the required
ns
settling time (t^)is 10 msec, then the natural frequency
(u ) is
n
“ ^ d f,
u = = 460 Rad/sec
n t 0.01
s
With assumed = 10 kohm, solving Eqs . (A. 12) and (A. 13)
for R^ and C gives
R^ = 20.5 kohm
C = 0.2954 F
To check if the calculated filter elements above
satisfy the transient response for the FM loop, we first
solve Eqs. (A. 7) and (A. 8) for and c to obtain
CO = 603 Rad/sec
n
5 = 0.983.
Then, from Fig. 14, the
Maximum overshoot = 18%
Settling time (t^) = 7.63 msec.
46
Obviously , the initial requirements of the transient
response are met also for the FM loop.
5 • Station Programming Circuit
As mentioned in the specifications of the MM 55110,
selection of a channel can be accomplished by external
electronic programming of the programmable divider. The
main consideration in designing the programming circuitry
is to obtain a fast and correct response from the channel
selection switches with a division number provided at the
inputs of the MM 55110. The station programming circuitry
consists of six parts.
a. Selection Switches
Switches provide appropriate logic levels to
IC's for the desired loop (AM and FM) and channel number.
An array of ten pushbutton switches represents the decimal
numbers 0 through 9. Selection of one channel from the
100 possible channels in FM or 111 channels in AM is accom-
plished by first resetting the channel to 000 with the push-
button station reset switch, and then by pressing in sequence
the pushbutton switches representing the digits of the de-
sired 3 digit channel number. For example, to select station
59, press switch labeled 0, then that labeled 5 and then the
one labeled 9 . An AM/FM switch selects either the AM or the
FM loop.
b. Switch Debouncing
Unpredictable outputs of the switches due to
switch bouncing are avoided by using RS latches to debounce
47
the switches electronically. Each time a switch gets pressed,
the debouncing circuit gives only one high-to-low pulse to
the encoder. The RS latch debouncing circuit is shown in
Fig. 15.
c . Encoder
The encoder transforms the decimal value of the
channel selection switch to a four bit BCD number and passes
the 3 decimal digit channel number through 3 latches where
it is used as an address to the PROM.
d. Shift Register and NAND Gate
To select the 3 digit channel nxamber, the same
channel selection switches and the ecnoder are used three
consecutive times. After every digit, the output of the
encoder is stored in a different latch to allow the next
digit to be transferred to the encoder. Enabling only one
latch at a time is accomplished by the shift register and
the NAND gate. The NAND gate gets four inputs from the
encoder and one input from the channel selection switch "0".
Its output is the clock signal to the shift register. Also,
serial data to the shift register is always "1". The shift
register can be cleared by the station reset switch. The
enable lines to the latches are taken from the first three
outputs through inverters. Fig. 16 represents this circuitry.
First, the shift register is cleared and that enables all
the latches. . Secondly, whenever one of the channel selection
switches is pressed, the NAND gate activates the shift register
48
+ 5V
1 .IK
Fig. 15. SWITCH DEBOUNCING CIRCUITRY
TO THE ENABLES OF THE LATCHES
reset switch
Fig. 16. TIMING CIRCUITRY
49
so that the data "1" is applied to the shift register.
Although the first decimal digit of a channel number is
taken as data to all altches, as soon as the switch is
released, the first latch retains the data while the others
are returning to the decimal digit "0". The next time, the
second and third latches take the second digit determined by
the pressed switch, but only the second latch holds the data
Finally, the third digit is received by only the third latch
Latch enabling order and the system timing diagram are shown
in Fig. 17.
e. Latches
Latches are used to hold the BCD value of each
channel number digit until another channel is selected.
The encoder and latch circuitry are shown in Fig. 18.
f. Programmable Read Only Memory (PROM — 1024x8)
The PROM serves as a Table Look-up, and it has
the outputs of the latches as an address . It converts the
channel number in BCD to the corresponding division number.
The product of that number and the reference frequency is
the AM output frequency corresponding to that particular
channel number. In FM, the multiplication also includes the
fixed modulus P which is 20.
The channel numbers used for AM and FM are the
same. With the use of the same reference frequency, the
division numbers out of the PROM must be different for the
AM and FM frequencies. That distinction is achieved by
50
Fig. 17. TIMING DIAGRAM FOR CIRCUITRY OF FIG. 16
51
vD
CO
CQ
<
2
&3
o:
u
8h
M
:s Eh
cn H
D
W U
Eh M
U
2
O U
^ 2
&4 M
a
cn
Eh
D
01
2
>•
cci
H
D
CJ
0^
H
CJ
n:
u
Eh
<
Q
3
<
a;
w
Q
o
u
3
w
52
Fig. 18. THE
applying "1" for FM and "0" for AM to the most significant
bit of the PROM address. That makes the first 512 addresses
available to AMand the second 512 addresses to FM. The
block diagram of the PROM (2708) is shown in Fig. 19.
g. BCD/7 — Segment Decoder/Drivers and Displays
There are three decoder /driver and display groups.
They display the three digit channel number chosen by the
channel selection switches. The first display group is
designed in a way such that it can display either the digit
zero or one, which is all that is needed for the first digit
of the channel number. The second and third groups are
capable of displaying the niombers 0 through 9.
53
TO THIi PROGRAMMABLE DIVIDER
o
0* o
< m
04 ^
o \ ^
r-l O
CN
tn
w
ac
o
w
ac
Eh
S
o
Pu
cn
D
04
5
H
o s
o: 04
04 \
S ac
Eh < U
D
0 » W M
2 E :2
H Eh cn
><
CEJ
Eh
M
D
O
»:
H
a
:s
o
ce;
04
ON
•H
04
54
IV. SUMMARY OF OPERATION AND PERFORMANCE CHARACTERISTICS
A. SYSTEM OPERATION
In this section, the operation of the synthesizer is
discussed. The subsystems are described in the preceding
chapter. Fig. 20 is a block diagram of the complete fre-
quency synthesizer with the programming circuit. Fig. 21
and Fig. 22 are the complete schematic diagrams of the syn-
thesizer and the programming circuit respectively.
In operation, programming the desired output frequency
is accomplished by setting the selection switches to the
appropriate channel number. The channel number is read
directly on the LED displays. Fig. 23 is a schematic dia-
gram of the display circuit. The variable division ratio N
is equal to .M for AM and equal to M.P for FM.
The synthesizer loop oerates as follows. The phase
detector compares the phase of the input signal with
that of the VCO signal divider output. The output voltage
of the phase detector, shwon in Fig. 24, passes through the
loop filter, which suppresses the high frequency components,
and then to the control element of the VCO which changes
its frequency in such a way that the phase difference be-
tween the input signal and the local oscillator output when
frequency divided by N is reduced. The synthesizer output
frequency is shown at various frequencies in Fig. 25 and
Fig. 26.
55
o
Fig. 20. COMPLETE BLOCK DIAGRAM OF THE PLL FREQUENCY
SYNTHESIZER
56
mm Ni '^A A injino n?
57
Fig. 21. SCHEMATIC DIAGRAM OF THE SYNTHESIZER
58
22. SCHEMATIC DIAGRAM OF THE PROGRAMMING CIRCUIT
■DH — |l'
59
Fig. 23. SCHEMATIC DIAGRAM OF THE DISPLAY CIRCUIT
LIST OF COMPONENTS
s
: 5
kfi
s
: 1
kfi
^3
: 51
kfl
:500
R.
0
:500
n
h
: 10
kn
s
: 20
.5 kQ
^8
through
R^7
:500
fi
^18
through
^21
: 2
kfi
^22
through
^25
: 1
kfi
Ss
through
^29
: 2
kft
^30
through
^33
: 1
kfi
^34
: 2
kfi
^35
: 2
kfi
Se
: 1
kfi
^37
: 1
kfi
‘"^38
through
^57
: 1
. 1 kO.
CO
in
; 1
kfi
‘^59
: 1
kQ
: 0.001 liF
: 0 . 1 ]iF
: 4.7 uF
; 0.001 UF
: 0 J. yF
Cg : 5 yF
: 0.1 yF
C„ : 0.001 yF
o
Cg : 0.1 yF
So = pF
: 0.3 yF
: MV 1404
: MV 1404
: MV 1404
: RF coil (200 yH - 400 yH)
L_ : Micro Metal Toraidal
^ Core #T30-22
5 turns of #20 copper
wire
60
Fig. 24.
OUTPUT OF THE PHASE DETECTOR AT LOCK
(Ch. Ill AM, Horizontal: 0.1 ms/div. ,
Vertical: 2 V/div.)
61
Channel 001
Frequency =
Horizontal ■
Vertical =
Channel 055
Frequency =
Horizontal
Vertical =
Channel 110
Frequency =
Horizontal
Vertical =
Fig. 25. OUTPUT OF THE AM VCO
955 kHz
1 usec/div.
.2 V/div.
1495 kHz
1 psec/div.
.2 V/div.
2055 kHz
1 usec/div.
.2 V/div.
62
^ A,
T.
■^> ■ 4. . .'H
r
■ - ■¥
-
•
•
M V
V >, V
V
f
I I I i i ' \ I I r
Channel 001
Frequency = 77
Horizontal = 0
Vertical = 0.5
Channel 050
Frequency = 87
Horizontal = 0
Vertical = 0.5
T \ ♦ I I I I <■ I
Channel 100
Frequency = 97
Horizontal = 0
Vertical = 0.5
Fig. 26, OUTPUT OF THE FM VCO
4 MHz
01 usec/div
V/div.
2 MHz
01 psec/div
V/div.
2 MHz
01 psec/div
V/div.
63
The FM VCO signal at is divided by a fixed modulus
P and downconverted before it is applied to the variable-
ratio divider. This operation is shown in Fig. 27 and Fig. 28.
AM and FM station local oscillator (LO) frequencies are
given in Table I and Table II respectively.
B . EXPERIMENTAL RESULTS
The performance characteristics of the digital phase-
locked loop frequency synthesizer are summarized in Table III.
As shown in the output frequency section of Table III,
the output frequencies are off of the desired frequencies
in proportion to the accuracy of the center frequency of the
reference. However, that much difference does not cause
any problem in the IF amplifier bandwidths of 10 kHz for
AM and 200 kHz for FM. Stability of the output was deter-
mined only in short time intervals (less than two hours) , and
was found to be r30 Hz for AM and ±400 Hz for FM for the
breadboard circuit.
The second harmonic of the AM output frequency is 30 db
down from the fundamental as seen in Fig. 29. The presence
of this second harmonic can result in the reception of un-
desired strong stations especially in the first eight
channels (up to 1025 kHz) . In conventional AM radio re-
ceivers, a radio frequency filter precedes the mixer. The
filter center frequency is shifted as the receiver is tuned
in order to avoid reception of "image" stations. Such radio
frequency filtering will also suppress reception of unintentional
64
Channel 001 FM
Frequency = 7.74 MHz
Horizontal = 0.1 ysec/div
Vertical = 1 V/div.
Fig. 27. OUTPUT OF THE MC 12012 SHOWN IN FIG. 13
Fig. 28. OUTPUT OF THE MC 3060 SHOWN IN FIG. 13.
65
_A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
D_
120 5
1215
1225
1235
1245
1255
1265
1275
1285
1295
1305
1315
1325
1335
1345
1355
1365
1375
1385
1395
1405
1415
1425
1435
1445
1455
TABLE I
AM STATION LO FREQUENCY GENERATION
Table Contents :
A. Channel Number
3 . Address to the PROM (Hex)
C. Memory Content (Hex)
D. Output Frequency ()<Hz)
B
C
D
A
B
C
000
CF
2075
26
026
78
001
5F
955
27
027
79
002
60
965
28
028
7A
003
61
975
29
029
7B
004
62
985
30
030
7C
005
63
995
31
031
7D
006
64
1005
32
0 32
7E
007
65
1015
33
033
7F
008
66
1025
34
034
80
009
67
1035
35
035
81
010
68
1045
36
036
82
Oil
69
1055
37
037
83
012
6A
1065
38
038
84
013
6B
1075
39
0 39
85
014
6C
1085
40
040
86
015
6D
1095
41
041
87
016
6E
1105
42
042
88
017
6F
1115
43
043
89
018
70
1125
44
044
8A
019
71
1135
45
045
8B
020
72
1145
46
046
8C
021
73
1155
47
047
8D
022
74
1165
48
048
8E
023
75
1175
49
049
8F
024
76
1185
50
050
90
025
77
1195
51
051
91
66
A
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
TABLE KCont.)
B
C
D
A
B
C
D
052
92
1465
78
078
AC
1725
053
93
1475
79
079
AD
1735
054
94
1485
80
080
AE
1745
055
95
1495
81
081
AT
1755
056
96
1505
82
082
BO
1765
057
97
1515
83
083
B1
1775
058
98
1525
84
084
B2
1785
059
99
1535
85
085
B3
1795
060
9A
1545
86
086
B4
1805
061
9B
1555
87
087
B5
1815
062
9C
1565
88
088
B6
1825
063
9D
1575
89
089
B7
1835
064
9E
1585
90
090
B8
1845
065
9F
1595
91
091
B9
1855
066
AO
1606
92
09 2
BA
1865
067
A1
1615
93
093
BB
1875
068
A2
1626
94
094
BC
1885
069
A3
1635
9 5
09 5
BD
1895
070
A4
1645
96
096
BE
1905
071
A5
1655
97
097
BE
1915
072
A6
1665
98
098
CO
1925
073
A7
1675
99
09 9
Cl
1935
074
A8
1685
100
100
C2
1945
075
A9
1695
101
101
C3
19 55
076
AA
1705
102
102
C4
19 6 5
077
AB
1715
103
103
C5
1975
104
104
C6
1985
105
105
C7
1995
106
106
C8
2005
107
107
C9
2015
108
108
CA
2025
109
109
CB
2035
110
110
CC
2045
111
111
CD
2055
67
_A
0
1
2
3
4
5
6
7
9
9
10
11
12
13
14
15
16
17
10
19
20
21
22
23
24
TABLE II
FM STATION LO FREQUENCY GENERATION
Table Contents:
A
B
C
D
B
Channel Number
Address to the PROM (Hex)
Memory Content (Hex)
Output Frequency (MHz)
CD A B
C
D
200
82
77.2
25
225
9B
82.
. 2
201
83
77.4
26
226
9C
82.
. 4
202
84
77.6
27
227
9D
82.
. 6
203
85
77.8
28
228
9E
82 .
.8
204
86
78.0
29
229
9F
83,
.0
205
87
78.2
30
230
AO
83,
. 2
206
88
78.4
31
231
A1
83.
. 4
207
89
78.6
32
232
A2
83.
. 6
208
8A
78.8
33
233
A3
83.
.8
209
8B
79 .0
34
234
A4
84,
.0
210
8C
79.2
35
235
A5
84 ,
. 2
211
8D
79.4
36
236
A6
84.
. 4
212
8E
79.6
37
237
A7
84 .
.6
213
8F
79.8
38
238
A8
84 ,
.8
214
90
80.0
39
239
A9
85,
.0
215
91
80.2
40
240
AA
85.
, 2
216
92
80.4
41
241
AB
85.
. 4
217
93
80.6
42
242
AC
85.
,6
218
94
80.8
43
243
AD
85.
.8
219
95
81.0
44
244
AE
86.
,0
220
96
81.2
45
245
AF
86.
,2
221
97
81.4
46
246
BO
86.
,4
222
98
81.6
47
247
B1
86.
.6
223
99
81.8
48
248
B2
86 ,
.8
224
9A
82.0
49
249
B3
87,
.0
68
A
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
TABLE II (Cont.)
B
C
D
A
B
C
D
250
B4
87.2
76
276
CE
92.4
251
B5
87.4
77
277
CF
92.6
252
B6
87.6
78
278
.DO
92 . 8
253
B7
87.8
79
279
D1
93.0
254
B8
88.0
80
280
D2
93.2
255
B9
88.2
81
281
D3
93.4
256
BA
88.4
82
282
D4
93.6
257
BB
88.6
83
283
D5
93.8
258
BC
88 . 8
84
284
D6
94.0
259
BD
89.0
85
285
D7
94.2
260
BE
89 . 2
86
286
D8
94.4
261
BF
89.4
87
287
D9
94.6
262
CO
89.6
88
288
DA
94.8
263
Cl
89.8
89
289
DB
95.0
264
C2
90.0
90
290
DC
95.2
26 5
C3
90.2
91
291
DD
95.4
266
C4
90.4
92
292
DE
95.6
267
C5
90.6
93
293
DF
95.8
268
C6
90.8
94
294
EO
96.0
269
C7
91.0
95
295
El
96 . 2
270
C8
91.2
96
29 6
E2
96.4
271
C9
91.4
97
297
E3
96.6
272
CA
91.6
98
298
E4
96.8
273
CB
91.8
99
299
E5
97.0
274
CC
92.0
100
300
E6
97.2
275
CD
92.2
69
TABLE III
CHARACTERISTICS OF THE SYNTHESIZER
Characteristics
Remarks
1 . Frequency Range ;
955 kHz to 2055 kHz (AM)
77.4 MHz to 97.2 MHz (FM)
1. Tunable in 10 kHz steps in
AM and 200 kHz steps in
FM.
2. Frequency Selection:
Electronically tuned
3. Output Waveform:
Sine wave
4. Reference Frequency:
f , = 5.00011 kHz
ref
2. The synthesizer is tuned
by an electronic pro-
gramming circuit actuated
by pushbutton switches.
3. Output voltage (AM)^ 0.8
volts peak-to-peak
(Fig. 25) . Output
voltage (FM)^ 1.5 volts
peak-to-peak (Fig. 26) .
4 . Center frequency of the
crystal oscillator is
10.240255 MHz (measured).
The crystal temperature
coefficient is 10 ^
parts/°C .
5. Output Frequency:
Ch.OOl (AM) = 955.321 >Hz ± 20 Hz
Ch.055 (AM) = 1495.032 kHz ± 30 Hz
Ch.in (AM) = 2055.045 kHz ± 25 Hz
Ch.OOl (EM) = 77.40169 MHz ± 300 Hz
Ch.050 (FM) = 87.20197 MHz ± 350 Hz
Ch.lOO (EM) = 97.20214 MHz ± 400 Hz
5.
The AM output frequency
is given by:
f ^ = N X f
out ref
= M X 5 . 0011 kHz
The FM output frequency
is given by:
f ^ = N X f
out ref
= M X p X f
ref
= M X 20 X 5.00011 kHz
70
TABLE III (Cont.)
6. Short Term Stability:
Ch.OOl (AM) = 0.0042%
Ch.055 (AM) = 0.0040%
Ch.11,1 (AM) = 0.0024%
Ch.OOl (FM) = 0.00077%
Ch.050 (FM) = 0.00080%
Ch.lOO (FM) = 0.00082%
7. Power Requirements:
Vcl = +5 volts
Vc2 = +8 volts
Vc3 = +5 volts
Vc4 = -5 volts
Vc5 = +12 volts
6. The short term stability
is given by: ^
of output frequency where
Af is defined as total
variation of the output
frequency
7. See Fig. 21, Fig. 22
and Fig. 23.
8 .
Spurious Level:
Ch.OOl (AM) = -30 db
Ch.055 (AM) = -30 db
Ch.lll (AM) = -38 db
Ch.OOl (FM) = -48 db
Ch.50 (FM) = -45 db
Ch.lOO (FM) = -46 db
(second harmonic)
(second harmonic)
(second harmonic)
(3.87 MHz off of the f , )
out
4.36 MHz off of the f J
out
(4.86 MHz off Of the f ^)
. out
Photographs of the output spectrum at various channels
are shown in Fig. 29 and Fig. 30. They are taken from a
Hewlett Packard Spectrum Analyzer model 141A with plug-in
units 8553 B RF section, 8552 A IF section, and 141S
display section.
71
r I f I * 1 T f
Channel 001
Frequency = 955 kHz
Scan Width = 0.5 MHz/div
Bandwidth = 100 kHz
Vertical = 10 db/div.
Channel 055
Frequency = 1495 kHz
Scan Width = 0.5 MHz/div
Bandwidth = 100 kHz
Vertical = 10 db/div.
1 4 I I < 1 J
Channel 110
Frequency = 2055 kHz
Scan Width = 0.5 MHz/div
Bandwidth = 100 kHz
Vertical = 10 db/div.
Fig. 29. SPECTRUM OF THE AM VCO OUTPUT
72
Channel 001
Frequency = 77.4 MHz
Scan Width = 2 MHz/div
Bandwidth = 300 kHz
Vertical = 10 db/div.
Channel 050
Frequency = 87.2 MHz
Scan Width = 2 MHz/div
Bandwidth = 300 kHz
Vertical = 10 db/div.
Channel 100
Frequency = 97.2 MHz
Scan Width = 2 MHZ/div
Bandwidth = 300 kHz
Vertical = 10 db/div.
Fig. 30. SPECTRUM OF THE FM VCO
73
stations caused by the second harmonic of the frequency
synthesizer output.
In conventional AM radio receivers, to shift the center
frequency of the radio frequency (RF) filter, the capaci-
tance of the filter is varied by turning the shaft of the
tuning knob. In the receiver which utilizes a PLL frequency
synthesizer, the voltage out of the phase detector can
replace the tuning knob to provide a control voltage to
vary the capacitance or resistance of a radio frequency
filter .
74
V. CONCLUSIONS
The proposed design of the system was successfully
implemented. Individual blocks of the system were designed
and built on a breadboard. The AM and FM synthesizer
operated as intended. A picture of the breadboard system
is shown in Fig. 31.
The use of integrated circuits is important. These IC
chips provide for system portability due to their small
sizes and power requirements . The circuit power can be
supplied by batteries. The ruggedness of IC's reduces
susceptibility to damage, and their low cost keeps the
overall system price low. The VCO ' s have exceptional
stability, and the digital PLL provides a means of frequency
synthesis with a higher degree of stability than can be
obtained with the use of some other frequency synthesizers.
It was found that using an LSI chip was very useful,
because the reference frequency divider and the programmable
divider in the MM 55110 did not introduce phase noise into
the loop because they are contained in a shielded package.
The spurious outputs at the FM VCO output are caused
by interference from the output of the MC 3060 -7 2 IC.
This interference can be reduced with shielding. Overall,
the fabrication of this synthesizer should have the following
features :
75
Fig. 31. THE BREADBOARD SYSTEM OF THE SYNTHESIZER
76
(1) Shielding of internal circuits to prevent inter-
ference with other circuits and to prevent energy leakage
to the outside environment.
(2) Isolation of various circuit stages to prevent
undesirable feedback and coupling.
(3) Power line filtering to attenuate propagation of
RF signals .
(4) Using a separate ground bus for digital and analog
circuits .
(5) Well regulated power supplies with filtering
to remove AC signals from the power bus.
77
APPENDIX A
DESIGN THEORY
Basically, a digital frequency synthesizer is a frequency
source whose output is an integer multiple of an input
reference frequency. A phase- locked loop (PLL) circuit
provides stable operation. The basic components of a phase-
locked loop frequency synthesizer, shown schematically in
Fig. Al, are the voltage controlled oscillator (VCO) , phase
detector (PD) , lowpass filter and programmable divider.
In Fig. Al,
= Conversion gain of the phase detector (Volts/Rad. )
Kq = Conversion gain of the VCO (Rad./Volts-sec)
= Input signal frequency (Rad. /sec)
*^(S) = Input signal phase (Radians)
<5^(S) = Error signal phase (Radians)
= Output signal frequency (Rad. /sec)
4>^(S) = Output signal phase (Radians)
F(S) = Transfer function of the loop filter
The transfer function of the system shown in Fig. Al
IS
H(S)
S + F(S)
KoKdF(S)
(A-1)
78
PHASE
DETECTOEI LOOP FILTER VCO
^ hn -H
a.
o
o
Q
w
u
0
1
w
c/3
<
pr{
o.
?
[I4
O
CD
<C
M
Q
u
O
h-:}
CQ
U
CO
<
a
<
t
•H
C14
79
Further,
1 - H(S)
S + K^KqF(S) [i-D
(A- 2)
Before proceeding further, it is necessary to specify
the loop filter F(S) . Its task is to attenuate fast changes
in phase error due to noise in the input signal; it also
helps to smooth out the high-frequency components of the
phase detector output and feeds DC control voltage into VCO.
A high degree of attenuation on high frequency components is
possible by making the lowpass filter bandwidth narrow. The
narrow bandwidth also reduces the noise fed into the VCO,
resulting in a good spectral purity at the VCO output.
However, if the bandwidth becomes too small, the loop will
not be able to acquire lock. A trade-off should be done to
satisfy these conditions. In this project a phase-lag-lead
filter was used, as shown in Fig. A2 ,
A/VV
c
Fig. A2. PHASE-LAG-LEAD LOWPASS FILTER
80
The transfer function of this filter is:
F(S)
l+STj
1 + ST,
where
(A- 3)
Ti = C(R^ + R^) (A-4)
= CR^ (A- 5)
When substituting in Eq. (A-1) , the loop transfer function
becomes
K-K.
(ST^ + 1)
H(S)
9 1 Vn
-I — ^ r 1 + ^ ^ T 1 s + ^ ^
^ N ^2 ^ NT^
(A- 6)
Because the highest power of S in the denominator of the
transfer function is two, the loop is a second-order loop.
In this transfer function K, and K_ are fixed numbers asso-
d 0
ciated with the phase detector and VCO, and N is variable
between N . and N determined by the desired output fre-
quency. The system characteristics then will be determined
by the filter coefficients T, and T_ as usual. Both co ,
natural frequency, and Q, dampling factor, are particularly
important in determining the transient response and stability .
Comparing the denominator of the transfer function with the
normalized standard second-order characteristic equation,
2 2
S + 2?w S + oo , cj and Q can be found in terms of system
n n n
variables as:
81
(A- 7)
= /K-K./NT, (Rad. /sec)
n a U 1
? - i/N/T^K^K^U+T^ ^^1 (A-8)
From Eq. (A- 7) and Eq. (A-8) , and T 2 are found to
oe ;
Vo
N 0 ?
n
(A- 9)
= ^ -
2>
u
N
n
^d^O
(A-10)
In transient response, the desired overshoot and the
settling time between channels determine the damping ratio
and natural frequency respectively. Type two second-order
step response curves (Fig. 14) are used to specify and
;; . Each response is plotted as a function of normalized
time oj t. Once oj and ; are found, synthesis of the filter
is relatively straight-forward. Since = C(Rj^ + R 2 ) and
= CR 2 from Eqs . (A-9) and (A-10) , actual capacitor and
resistor values may be computed as:
R
R
C
2
1
2C
N
Coo CK,K_
n d 0
^d^O N _ 2c
2 CK .K,, Coj
CNoj d 0 n
n
N
R_0J R-KjK,,
2 n 2 d 0
(A-11)
(A-12)
(A-13)
82
must be used, since it
In these equations, N = N
^ max
represents the worst case (Maximum overshoot occurs at
N which is minimum loop gain) .
max ^ ^
83
s.
LIST OF REFERENCES
1. Manassewitsch , V., Frequency Synthesizer Theory and
Design , Wiley, 1976.
2. Signetics Corporation, Analog Applications Manual ,
Uniplar .
3. Motorola Semiconductor, Epicap Tuning Diode Theory
and Applications, Technical Information Note AN. 178 A.
84
BIBLIOGRAPHY
Berlin, H.M., Design of Phase-Locked Loop Circuits with
Experiments , Sams, 1978.
Gorski, Popiel, J., Frequency Synthesis; Techniques and
Applications , IEEE, 1975.
Kroupa, V.F., Frequency Synthesis , Wiley, 1973.
Manassewitsch, V. , Frequency Synthesizer Theory and Design
Wiley, 1976.
Motoryla Semiconductor, Epicap Tuning Diode Theory and
Applications , Technical Information Note AN. 178 A.
Motorola Semiconductor, MC 12012 Data Sheet .
Motorola Semiconductor, MC 1648 Data Sheet .
National Semiconductor, MM 55110 Data Sheet .
Signetics Corporation, Analog Applications Manual , Uniplar
85
INITIAL DISTRIBUTION LIST
No. Copies
1. Defense Technical Information Center 2
Cameron Station
Alexandria, Virginia 22314
2. Library, Code 0142 2
Naval Postgraduate School
Monterey, California 93940
3. Department Chairman, Code 52 2
Department of Electrical Engineering
Naval Postgraduate School
Monterey, California 93940
4. Assoc. Professor G.A. Myers, Code 62Mv 10
Department of Electrical Engineering
Naval Postgraduate School
Monterey, California 93940
5. Assoc. Professor G.D. Ewing, Code 62Ew 1
Department of Electrical Engineering
Naval Postgraduate School
Monterey, California 93940
6. Deniz Yuzbasi Nurettin Bal 1
Oyak Sitesi Blok; 36/8
Yenilevent - Istanbul - TURKEY
7. Deniz Yuzbasi Dogan Ozdemir 2
Dr. Fazil Gokceoren Sok. Lale Apt.
No: 20/7
Gdztepe, Istanbul, TURKEY
8. Deniz Kuvvetleri Komutanlugi 2
Egitim Dairesi
Ankara, TURKEY
9. Istanbul Teknik Universitesi 1
Elektrik Fakiiltesi
Gumiissuyu, Istanbul, TURKEY
10. Bogazici Universitesi 1
P. K. 2 Bebek, Istanbul, TURKEY
11. Orta Dogu Teknik Universitesi 1
Ankara, TURKEY
86
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09955 Ozdemir
c.l A digitally tuned
AM/FM radio.
191196
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