Document text
DESIGN AND FABRICATION OF AN
F. M. TRANSMITTER
A Thesis Submitted
In Partial Fulfilment of the Requirements
for the Degree of
MASTER OF TECHNOLOGY
BY
JAl KRISHNA GAUTAM
DEPARTMENT OF ELECTRICAL ENGINEERING
INDIAN INSTITUTE OF TECHNOLOGY KANPUR
OCTOBER 1971
CEHOTICATE
Certified that this work on "Design and Fabrication
of a F *M* Transmit ter” has been carried out und er my
supervision and this has not been submitted elsewhere for
a degree .
S ."Tehkateswaran
Professor
Department of Electrical Engineering
Indian Institute of Technology
Kanpur
APOOTOEDGEMBSO!
The author is most grateful to
Professor S. Venkateswaran for suggesting an
interesting topic for the pro j ect and for his
continued encouragement and guidance.
He is also thankful to the Electrical
Engineering Department for providing the
required facilities for completing this project.
TABES OF OOgrarTS
ABSTRACT viii
CHAPTER I : INTRODUCTION 1
CHAPTER XI: THEORY 3
2.1 Statement of the Problem 3
2.2 Principle of Working 3
2.3 Schematic Block Diagram 9
2.4 Functions of Different Blocks 9
CHAPTER III : DATA REQUIRED FOR DESIGN 14
3.1 Transistor CID 472 and CH 911 H
3.2 Diodes CD-21, CD-22 , CD-23 , CD-31 ,
CD-32, CD-33 H
3.3 Junction Capacitance Measurement
for Different Diodes 14
CHAPTER IV : DESIGN 23
4.1 Frequency Deviation Requirement
and Choice of Diode 23
4.2 Audio Amplitude Requirement 24
4.3 Calculation of Gain of Audio Stages 25
4.4 Design of Audio Stages 27
4.5 Design of Oscillator-cum-Modulator 37
4.6 Design of R.F. Amplifiers 39
4.7 Design of Frequency Multiplier Stages 43
4.8 Design of Coils and Transformers 46
4.9 Overall Circuit Diagram 50
V
CHAP 'USE V :
RESULTS
52
5.1
Carrier Erequoncy and Erequency
Stability
52
5. 2
Erequency Deviation
53
5.3
Power Output
53
CHAPTER VI :
CONCLUSION
58
APPEND IX -A :
GAIN OE CASCADED AUDIO AMPLIFIERS
59
APPEND IX-B :
CALCULATION CE REQUIRED POWER
62
BIBLIOGRAPHY
69
vi
liar OF TABLES
NO.
DESCRIPTION
PAGE NO.
3.1
Transistor Data
15
3.2
Diode Data
16
3.3
Diode C-Y Measurements
17
3.4
Diode Junction Capacitance vs. Reverse
Bias Voltage for CD-21
20
4.1
Tuned Circuit Inductances and Capacitances
for R.F, Amplifiers
45
4.2
Tuned Circuit Inductances and Capacitances
for Frequency Blultipliers
45
4.3
Tuned Circuit Inductances and Capacitances
for Different Tank Circuits
49
5.1
Results of Frequency Measurements
54
vii
LIST OF FIGURES
NO.
DESCRIPTION
PAC-E I
2.1
Normalized junction capacitance
of a typical varicap
8
2.2
Schematic block diagram of a
transmitter
10
3.1
Junction capacitance vs. reverse
bias voltage curves for diodes CD-
CD-22 ,and CD-23
-21,
18
3.2
Junction capacitance vs. reverse
bias voltage curves for diodes
CD-31 , CD-32 and CD-33
19
3.3
Junction capacitance vs. reverse
bias voltage curves for diodes
CD-21
21
4.1
Audio amplifier circuit
28
4.2
A typical single battery common
emitter amplifier stage
33
4.3
Low pass filter
33
4 *4
Osc dllator-cum-Modulator Circuit
40
4.5
R.F. Amplifier
42
4.6
Frequency Multiplier
44
4.7
Coil Data
48
4.8
Overall Circuit diagram
of the transmitter at 70.2 MHz
51
5.1
Junction capacitance vs. reverse
bias voltage on the diode
55
5.2
Oscillator Frequency vs. reverse
bias voltage on the diode.
56
rili
ABSTRACT
This thesis deals with the design and fabrication
of a solid state I'M transmitter. It mainly concerns with
the theory, design and experimental results that have been
obtained by vaiying the junction-capacitance of a reverse
biased diode, which is a part of the tank circuit of the
oscillator. The frequency has been multiplied by a factor
of fiftyfour to reach the desired frequency of transmission.
fclf. W
Power output of the transmitter is supposed to/receive
signals over a range of 2 KM. The novelty of the project
is, that no imported component has been used and all the
work has been carried out with indigenous components that
are available in the Indian Market .
The transmitter set can be used at one end for
short distance communication if a suitable receiver is
used at the opposite end. It. is helpful in Walkie-Talkie
equipment because the set is completely transistorised
and makes use of two six volts dry cell batteries as the
power source .
CHAPTER I
INTRODUCIION
She equipment that has been fabricated is useful
for short distance communications. A transmitter of
centre frequency seventy MHz has been designed and
fabricated. Modulation is effected by a varicap. Solid
state circuitry has been employed and the components that
are used are all indigenous ,
Chapter two of this report deals with the theory
of modulation 5 it has been shown how to get frequency
modulation when tank circuit capacitance of the oscillator
is varied in accordance with an audio signal. Audio signaL
varies the junction capacitance of a reverse biased diode
and hence the frequency of the oscillator tank-circuit.
Next, a schematic block diagram and description of
different blocks is given.
In Chapter three the necessary disign data is
given and also results of measurements carried out on
different diodes. The measurements concern with the
junction capacitance and reverse bias of the diode.
A diode CD-21 is chosen and detailed measurements
carried out.
Chapter four deals with the design of different
blocks of the transmitter circuit, such as oscillator,
frequency multipliers,R.I*'. amplifiers and also the coils
and transformers that have been used for tank circuits
and for interstage couplings. Design principles used are
very simple .
Results that have been obtained are given in
Chapter five. Details are given about the carrier fre-
quency, frequency stability of the carrier, frequency
deviation and the output power* Dhey almost match with
the requirements of the problem, frequency deviation
curve with respect to the reverse bias is also given.
Chapter six concludes the report.
CHAPTER II
THEORY
2 .1 Statement of the Problem
To design and fabricate a transmitter with
indigenous components with the following specifications:
i) Frequency seventy MHz.
ii) Power output sufficient to transmit signals upto
a distance of two kilometers.
iii) Modulation E.M. with a maximum deviation of
£75 KHz.
iv) Input audio at -72 dbm (0 dbm= 1 mW).
v) Solid state circuitry with modulation effected
by varicap .
2 *2 Principle of Working
The principle of working has been devided into
two sections, first one deals with the theory of
modulation and the second one shoy/s how it is achieved
by a varicap .
1
2.2.1 Theory of Modulation:
Generation of frequency modulated waves by varying
the capacitance of the resonant oscillator circuit is as
follows:
let, C(t) = variable capacitance of the resonant circuit
4
C(t) = C + £iC Sin w t
° m
( 2 . 1 )
where
C Q - capacitance in the absence of modulation.
6C = maximum change .
Instantaneous frequency w^Ct) is given by
w i M = ScTtT
Differentiating both sides
( 2 . 2 )
2w i (t) dw i (t)
DC^(t)
dw^(t)
-w-it
2cTT
Considering the variations to be small
A^(t) + N
(2.3)
where, &C(t) = AC Sin w^t .
Therefore ,
a p
w ± (t) = w 0 +Aw ± (t) = w Q (1 - I^Sin w m t) (2.4)
Similarly, if 0 is considered to be constant and the
inductance 1 is varied we obtain the expression
w ± (t) * w (1 - §~- Sin w t)
(2.5)
w ± (t) = w Q (1 + d ~- Sin w m t) = w 0 +Aw Sin w m t
we get,
Negative sign in equation (2.3) shows that
a) Increasing the capacitance decreases the
frequency, and
b) Decreasing the capacitance increases the
frequency.
In the next sub -section we will see how we get
this variation of tank capacitance from a reverse biased
diode (varicap ) .
2.2.2 Varicap:
Here frequency modulation is obtained by varying
the capacitance of the tank circuit of the oscillator in
accordance with the amplitude of the audio signal. The
capacitance variation of the tank circuit may be obtained
in many different ways and one out of them has been
2
employed .
In a junction diode if the reverse bias across the
diode junction is varied, the junction capacitance also
varies .
There is a dipole layer of chaige in the region of
any barrier, which is necessary to create the electric
field in the barrier region* If the voltage is increased
in the barrier region (reverse bias) the field Increases
in the barrier region and amount of charge in the dipole
layer must also Increase.
The number of ionised donors and therefore amount
of positive charge found in the depletion region of the
barrier is much greater for reverse-bias than for the
forward bias . If the charge in the depletion region
changes as the bias voltage changes, it is clear that a
barrier capacity must exist. The dipole layer here
consists of the unneutralised ionised impurity atoms
found in the depletion region of the junction barrier
and since the impurities are distributed in the volume of
the semiconductor, the thickness of the depletion region
must always increase as the charge and voltage increase .
That means junction capacitance between the terminals
decreases for the reverse bias and increases with the
forward bias .
Capacitance voltage characteristics of a typical
varicap look as depicted in Figure 2.1 .
Instantaneous change of capacitance with the
applied bias voltage is the most important feature of
varicaps. Capacitance as a function of bias voltage can
be expressed by the following equation for a reverse biased
varicap .
'T
°3
= c
JL2.
(1 +
bias.'
T~~
n
( 2 . 6 )
where
Crp = Total capacitance of varicap,
0^ = Package capacitance
Ch = Junction capacitance
C^ 0 = Junction capacitance at zero bias
^bies = -^-PPlied reverse bias
0 = Contact potential (function of the
semiconductor and doping level)
n = exponent of capacitance variation.
0 - 0.5 - 0.7 volts for silicon
=1.1 - 1 .2 volts for Gallium arsenide
n is a function of the junction type.
n =,1/2 for abrupt junctions)
) Ideally.
= 1/3 for graded junctions)
In actual device C-V characteristics can be
approximated by using a value of n between 0.28 - 0.45*
Assuming a typicaL capacitance-voltage function of
C.
0
(1
V. . .
bias
+ ~o75
~T/3
)
for a silicon diode .
(2.7)
Por the experiments carried out capacitance of
different diodes was measured at a number of discrete
bias voltages and then best was chosen. Practically, a
partial curve is used for the modulation such that it
8
Figure 2.1s normalised Junction Capacitance of a Typical
Varicap
gives almost a linear range of variation of capacitance
with respect to reverse bias voltage.
2 ,3 Schematic Block Diagram
The schematic block diagram of the circuit of a
suitable transmitter is given in Figure 2 .2 and is
described in the following pages.
2 .4 Functions of Different Blocks
If an oscillator is designed at high frequency
of seventy MHz (frequency under consideration) the
oscillator will have stability problems, A slight
variation in circuit components might change the working
frequency by quite a lot.
Therefore, the frequency which is being generated
by the oscillator, has been kept cU" a lower value such
as 1,3 MHz; and also is being frequency modulated at this
lower frequency only. Main reason being that at high
frequency the tank circuit capacitance itself Is very
small and a variation of very small amount will be needed
for the required frequencir deviation to achieve, which may
not be practicable.
The final frequency is obtained by using a series
of class , C f amplifiers in cascade tuned to the harmonics
of the input to act as fre quency multipliers .
Oscillator frequency ^1.3 MHz
Final frequency 70,2 MHz
10
Block
Ho .
1
2
3
4
5
6
7
8
9
10
he script ion
Frequency of
operation
Oscillator witty the tank circuit
- ■
Oscillator tank circuit and
Modulator circuit
1.3 MHz
R.F. amplifier
1.3 MHz
First frequency multiplier (x3)
3.9 MHz
Second frequency multiplier (x3)
11.7 MHz
Third frequency multiplier (x3)
35*1 MHz
Forth frequency multiplier (x2)
70.2 MHz
Power amplifier
70.2 MHz
Pre-amplifier (audio frequency)
Two audio amplifier stages and a low
pass filter.
Figure 2*2: Schematic block diagram of the
Transmitter *
11
Therefore, the multiplication factor required is fifty-
four which is obtained as (3x3x3x2 = 54).
2.4.1 Oscillator -cum-Modulator:
Oscillator is of Hartley type, using the transistor
in common base configuration, feedback is given from the
tapping of the tank circuit coil, which is in the collector,
to the emitter through a feedback capacitor. A reverse
biased diode is put in parallel with the tank-circuit of
the oscillator, for achieving frequency modulation, the
audio signal is fed to the reverse biased diode. This
varies the junction capacitance of the diode in accordance
with the amplitude of the audio signal and hence the
frequency of the oscillator.
A small portion of the C~V curve of the varicap
diode is made use of, such that it gives practically a
linear range of variation of frequency with respect to
the audio input signal. In the block diagram, block one
is the oscillator without the tank circuit associated
with it and block two contains the oscillator tank circuit
along with the modulator circuit, consisting of diode with
variable capacitance property.
2.4.2 Audio Amplifier and the low Pass filter:
There are three stages of amplification, first is
a common collector circuit which acts as a pre-amplifier
for the. audio signal. Since modulation is F.M., it may be
12
assumed that a moving coil microphone is used (for a good
quality of sound reproduction, capacitor microphone could
also be used), which has -72 dbm output and has an impedance
of say 600 ohms with a suitable transformer being used. How,
a common collector circuit with reasonably high impedance
as compared to the microphone impedance (600 ohms with
transformer) may be designed as has been done in
Section 4.4.1 . 'This circuit is indicated in block nine
of the schematic block diagram figure 2.2.
Hext, block number ten contains two R.C . coupled
common emitter stages to amplify the audio signal to the
required voltage level, which comes from the microphone
through the pre -amplifier . This level needed must be
proper for the reverse biasing of the diode that is put
in the modulator circuit. All these have been calculated
and used for design in Chapter lour.
low pass filter is used to isolate the oscillator
and audio stages such that the audio frequency signal can
go to the diode (reverse biased in the tank circuit of
the oscillator), but radio frequency cannot come to the
audio stages, otherwise, the audio frequency signal will
be superimposed by the radio frequency carrier, which is
not desirable.
2.4.3 Radio Frequency Amplifier:
Since the oscillator is made to oscillate at lower
voltage level, so that it may not affect the modulating
circuit, we need amplification of the signal, for feeding
it to the class ’O’ amplifier stage, which is being used
for frequency multiplication by tuning its output tank
circuit to the harmonics of the input frequency.
Block three radio frequency amplifier (operating
frequency 1 .3 MHz) is used in common emitter configuration
and under class 'A' conditions. Block eight also is in
common emitter configuration under class * G 1 operating
conditions. 'The operating frequencies of blocks three and
eight are approximately 1.3 MHz and seventy MHz respectively
2 .4 .4 Fre quency Multipliers :
These are essentially class f C f amplifier units
tuned to the harmonics of the fundamental's input fre-
quency, which are biased at zero bias voltages, such that
they operate in nonlinear range of transistor transfer
characteristics .
Blocks four, five, six and seven all are in common
emitter configuration. Input frequencies of these blocks
are 1.3 MHz, 3.9 MHz, 11 .7 MHz and 35.1 MHz respectively
and the output frequencies are 3.9 MHz, 11.7 MHz, 35.1 MHz
and 70.2 MHz respectively.
CHAPTER III
RATA REQUIRED EOR DESIGN
3.1 Transistor CID 472 and CR 91 1 3
The data given for the transistors that have been
used is given in Table 3.1 and also all the terms that have
been used in the tahLe are defined explicitely like, collector
to base voltage, emitter to base voltage, collector current
and so on .
3.2 Diodes CD-21, CD-22 . CD-23, CD-51 , CD-32, CD-33 4
The data given by the manufacturer for these diodes
is given in the next table, Table 3.2 and the terms are also
defined as in the case of transistors like peak inverse
voltage, operating current and so on.
3.3 J unction Capacitance Measurement for Different Diodes
Junction capacitance measurements are made on six
diodes, that are supposed to be the best junction diodes
for the purpose indicated earlier, which have been identi-
fied in Section 3.2.
Boonton capacitance bridge was used to perform the
measurements . This instrument works at the frequency of
100 KHz. There is a provision for applying both the reverse
and forward bias to the measuring terminals. There is also
a provision for measuring the direct and indirect capacitance
15
Table 3 .1
Transistor Data*
Transistor
CIL 472
GIL 91 t '
Specifications j
Application
Driver
Low level,
pre-
amplifier
low noise
amplifier
Collector base voltage, volts
25
32
Collector emitter voltage, volts
25
32
Emitter base voltage, volts
5
5
Average collector current , mA
75
60
Peak collector current, mA
150
150
Collector leakage current , iiA
0.7
0.1
Total dissipation at 25°C Amb
temp.mW 200
150
Transition frequency, MHz
10
350
* **
Current gain I =1 mA, V =10
volts
40-150
-
-X*
I =0.1 mA,¥ =10 volts
c ’ ceo
-
40-150
* I - Average collector current
V
** V - Collector emitter voltage
ceo
16
Table 3.2
Diode Data
ITo .
Type*
volts
T
-L
0
mA
mA
Z R
/U.A
P T
mW
1
CD -21
20
50
150
1
150
2
CD -2 2
50
50
150
1
150
3
CD-23
100
50
150
1
150
4
CD-31
20
50
150
0.1
150
5
CD-32
50
50
150
0.1
150
6
CD -33
100
50
150
0.1
150
* Silicon diodes
iv ” Peak inverse voltage
P o Operating current
I f m ~ Maximum forward current
p r ~ Reverse current
P I Dower dissipation.
17
Table 3.3
Diode. C- V Mea s urements
Junction capacitance in pi 1
J.IU «
type “
Reverse
bias
voltage
volts 1
CD-21
CD -2 2
CD-23
CD-33
CD-32
CD-31-
1
0.5
41 .8
41 .4
28.28
28.94
29.76
31.46
2
1 .0 '
35.0
33.82
22.10
22.76
23.24
24.74
3
1 .5
31 .7
29.59
18.70
19.66
20.14
21 .42
4
2.0
29.2
26.74
16.84
17.60
18.05
19.34
5
2.5
27.25
25.26
16.44
17.12
17.68
18.82
6
3.0
25.80
24.56
15 .38
16.01
16.52
17.71
7
3.5
24.70
23.60
14.50
15.60
15.70
16.90
8
4.0
23.70
22 .64
13.84
14.53
15.00
16.05
bO •
0 12 3
>- Severs e bias voltage
in volts
Figure 3.2 : Junction capacitance vs. reverse -bias
voltage curves for diodes CD-31, CD- 32 ,
and CD-33 .
Table 3
Diode Junction Capacit
bias voltage
Reverse bias Junction
Do. voltage in capaci-
volts tanee pD
o o
1
0.4
43.8
16
2
0.5
41.8
17
3
0.6
40.1
18
4
0.7
38.8
19
5
0.8
37.5
20
6
0.9
36.3
21
7
1 .0
35.0
22
8
1 .1
34.3
23
9
1 .2
33.5
1
24
10
1 .3
32.8
25
11
1 .4
32.2
26
12
1 .5
31 .7
27
13
1 .6
31 .05
28
14
1 .7
30.6
29
15
1 .8
30.0
30
20
Reverse bias
voltage in
volts
Junction
cap acitance
pF
1.9
29.6
2.0
29.2
2.1
28.75
2.2
28.35
2.3
28.02
2.4
27.6
2.5
27.25
2.6
27.0
2.7
26.7
2.8
26.45
2.9
26.2
3.0
25.8
3.1
25.5
3.2
25.2
3.3
24.95
Junction
Capacitance
in pi 1
o • j * Junction Capacitance vs* reverse bias
voltage curve for diode CD-21 .
22
of the sample. Direct and indirect mean grounded and
ungrounded capacitance. The diodes were connected to the
instrument and the reverse bias was applied and direct
capacitance (grounded capacitance) measurements were
performed at different discrete bias voltages and then
the curves were plotted. The results of the measurements
are given in Table 3.3 and capacitance vs. reverse bias
voltage curves have been plotted in Figures 3.1 and 3.2.
From the curves of junction capacitance vs. reverse
bias voltage of different diodes it was found that the
curves for CD-21 will give the best results out of the
lot that has been taken for measurements and hence
detailed measurements were made and then it was found
quite suitable for the purpose of using in the circuit.
Why this particular diode was taken for the circuit
will be clearer in Section 4.1. The detailed measurements
are given in Table 3.4 and a precise curve has been
plotted in Figure 3.3.
CHAPTER IV
DESIGN
4 . 1 Frequency Deviation Requirement and Choice of Diode
The desired frequency deviation at 70.2 MHz carrier
is +75 KHz as specified in the problem and then we can cal-
culate the frequency deviation at 1 .3 MHz, our starting
f re quency .
Frequency Deviation at 1 .3 MHz = + ( 75x tjr^ ' g ) *=* +1 .4 KHz
Therefore frequency deviation needed at 1 .3 MHz is
+1,4 KHz. How, desired value of capacitance variation of
the tank of the oscillator circuit may be calculated as
follows. From equation (2.3)
a£
20 .
o
A w
A-f
-f„
(4.1)
where
Af =r 1 .4x1 0 3 Hz
f 0 ^ 1 ,3x10 6 Hz
Therefore
AG = 2 . 1 5 x 1 0~ 3 C n
and 2 aG = 4 .3x1 0 ” 3 C Q
How, to get proper amount of frequency deviation
from the variation of junction capacitance of the diode
we must calculate the tank circuit inductance and
capacitance .
As discussed in later sections, the inductance of
the tank circuit is kept at approximately 20 yuH and hence
the capacitance is calculated at 1.3 MHz carrier.
1 = 20 /uH
f = 1 . 3 MHz
We know,
f =
1
2T^/m
(4.2)
From this : value of ’O' comes out to be approximately 749 pF
by using the above equation (4.2).
How, the required value of 2&C may be calculated
from equation (4.1) using (C = 749 pF).
2 aC = 4. 30x1 0" 3 C 0
or 2 AC. = 3.2 pF
From the curves of diodes drawn in Figures 3.1 and 3.2,
it was found that, for this much of capacitance variation,
the curve for diode CD-21 gives approximately a linear
range of variation of 3.2 pF for reverse bias (diode biased
at 1.8 volts negative) and it suits the best.
That is why, diode CD-21 was used as the circuit
element for the modulator circuit.
4 .2 Audio Amplitude Requirement
The bias of the diode must be such that we get
practically a linear range of variation of junction
capacitance with respect to the reverse bias voltage
applied. From the curve of Figure 3.3, we find that the
best point for biasing it, will be approximately at
1 .8 volts. At this bias a variation of 3.2 pF may be
obtained by varying the bias from approximately equal to
1.5 volts to approximately equal to 2.1 volts, and therefore,
the audio signal that is modulating the carrier at 1 .3 MHz
should be the difference of the two, peak to peak ( that is
approximately equal to 0.6 volts).
How, we are in a position to calculate the gain of
audio amplifier stages .
4 . 3 Calc ul ation of G-ain of Audio Stages
From Section 2.1 as stated in the problem
Input from microphone is at -72 db>n( 0 dhwp 1 mW) .
db = 101og 10 (P.[/P 2 ) (4.3)
where P 2 =1 mW
-72 = 101og 10 (P-,x10 3 )
From this we find that P-| = 63.1x10”"^ watts.
We have calculated the input po?fer, to the audio
amplifiers through the microphone , but we want to calculate
the voltage gain, which will be useful in finding out the
gain of the audio stages and with the help of which then
we will be able to find out the input voltage to the audio
pre -amplifier .
As indicated in Section 2.4.2 we are using a moving
coil type of microphone and whose impedance with suitable
transformer is assumed to be 600 ohms.
Taking all these considerations into account, we
can calculate the input voltage.
Power input P-j = 63.1 pH
Impedance R = 600 ohms
Since
P = V 2 /R (4.4)
where P - Input power,
V - Input voltage and
H - Input resistance.
V = y^3T = 0.2 mV
Hence, the input voltage is 0.2 mV r.m.s approximately.
Prom section 4.2,
Output voltage needed = 0.6 volts peak to peak
0.6 volts peak to peak= 0.21 volts r.m.s.
Hence, the voltage gain of the audio stages is G- and
given by
r _ Output voltage _ 0.21x10^ ^ 1 1 nn
v “ Input voltage 0.2 r
Therefore ,
Voltage gain = 1,100 (4.5)
This will be useful later in designing the audio stages .
27
4 .4 Design of Audio Stages
The audio voltage gain required is approximately
1,100 as calculated in the above section. Amplifier is
split into three stages. One pre -amplifier and two stages
of amplification using R-C coupling. The gain adjustment
may be done by a potentiometer that has been put in inter-
mediate stage and the gain can be adjusted to a desired
value .
Feedback has not been employed for simplicity of
design and to avoid the complexities in calculations and
performance of the amplifier stages. The design equations
are very straightforward as given in later sections of
this chapter.
4.4.1 Pre-amplifier Design:
The pre-amplifier does not load the microphone
connected at the input and also it isolates it. Transistor
OIL 472 is used. We shall be using following biasing equations
as given for a common collector circuit in Figure 4.1 .
According to the circuit diagram we shall be calculating
the values of bias resistors and the voltages at different
points .
*1*1 = < Y CC ' V BS> ~ (I e S e or W
I 2 E 2 = V BE + I 3 E 3
*1 “ X 2 - X b
and Base Resistance, R^ = R-jR 2 /(R-j+R 2 )
(4.6)
(4.7)
(4.8)
(4.9)
28
Rj =36 K-~ohms
Eg = 12 K-ohms
Ij = 1 K-ohm
R^ = 51 K-ohms
R.^ = 15 K-ohms
Eg = 4.7 K-ohms
Ry = 1 .5 K-ohms
Rg = 51 K-ohms
R^ ss 15 K-ohms
R-j q= 4.7 K-ohms
R^-j =1.5 K-ohms
=10 yhP 6V
Og = 10 /UP 6V
C 3 = 10 /dS 6V
= 10 67
C 5 = 100 yuE 67
Cg = lOO^/uR 67
T 1 = 2 2 = T 3 = 0IE472(EPSr)
Figure 4.1: Audio amplifier circuit.
29
We are using six volts battery and therefore,
V CC = ^ v °l' ts *
lor a Silicon transistor ? BE is of the order of 0,5 volt
and therefore, we can take this approximate value for our
calculations .
T-g-g =0,5 volt
Assuming a reasonable current (1 mA) in the emitter and a
drop of one volt across the emitter resistance R*, such
;hat Y ,
'CE = V C0 " = 5 »0 volts, R^ comes out to be one
kilo-ohm.
Erom equation (4.6),
I-j R-| =4.5 volts
(4.6a)
and from equation (4.7),
R 2 R 2 = volts
(4.7a)
Eor a good stability with respect to temperature variations
and in turn variations in reverse collector current (I co )
the stability factor should be approximately 10, as given
in standard text-books .
R b
S ^ 1 + gS. for Re » R-O-rf) (4.10)
e
from this R^ can be calculated for
S s 10 and R_ = 1 K-ohm.
e
It comes out as R^ = 9 K-ohms approximately.
Row, from equation (4.9),
Rjj = 9 K-ohms s= ’(4.9a)
30
T .7e conveniently choose the value of R-j and Rg from
equations (4.6a) and (4.7a).
I-jR-| =4.5 volts
I 2 R 2 = 1 .5 volts
for the convenience of. calculations we can neglect
in comparison with 1^ and I 2 and then, we get,
3 (4.1*1)
from equations (4.9a) and (4.11) we calculate the values
of R-j and R 2 . They come out as
R-j = 36 K-ohms
R 2 = 12 K-ohms
So, the design values for bias resistors are as follows:
R-j =36 K-ohms , Rg = 1 2 K-ohms , R^ = 1 K-ohm
and also
Tr f R 2 II ** R 3 W
Y B - ( (R 2 |j £R 3 J+R-j ) T CC - * 3 TolXS
( 4 . 12 )
The coupling capacitors C-j and C 2 (at the input ard
output of the pre-amplif ier ) are designed such that they
pass all the desired frequencies in the audio frequency
range and disconnect the d.c, supply from going from one
stage to the other. Actually, they limit the low frequency
response of the amplifier and are chosen to be 10/UF in
value .
Since, we are interested in voltage gain of these
amplifiers, we can readily see that a common collector stage
gives a voltage gain of approximately unity ,
(4.13)
Voltage gain of an amplifier is given
r
v ” Jj i +h 22 ( 1 -S
where, 1 h 11)T1 are the 'h* parameters for the given transistor
and S is the ratio (S = h-j 2^2 1^22^ w hi- c h is a measure of
the effect that h-j2 has on the performance of the transistor.
It is a measure of how much the load affects the input
impedance and how much the source affects the output
impedance .
Voltage gain of all three stages has been calculated
in Appendix -A, by using approximate 'h' parameter of a
typical low frequency, small signal transistor.
4.^.2 R-C Coupled Audio Stages:
Voltage gain of a common emitter amplifier is given
by (approximately)
T ~ r e +r t 0 -cO (4,U)
where ,
R-^ = load resistance
o< = Common emitter current amplification factor
r = emitter resistance of the transistor
and r^= base resistance of the transistor.
The amplifier is designed for a overall voltage
gain of more than the required value (required vaLue of
voltage gain as calculated in Section 4.3 is 1,100) and
then the gain is adjusted by a variable resistance as given
in diagram of Figure 4.1 V
32
The movable element of the potentiometer is
connected to the preceding stage. Thus when the gain is
changed, the d.c, resistance from base to ground is
maintained constant and there is no change in the bias of
the stage. Since the output resistane of the preceding
stage is generally, much higher than emitter, the
resistance of the potentiometer or the transistor input , cenrt
the frequency response of the two stages is practically
independent of the gain control setting.
Feedback is not employed in this circuit for
the convenience of design and calculations and moreover
without feedback also, this circuit gives quite good
stability and frequency response.
Knowing all this we will decide on the value of
the biasing elements in the circuit . The design equations
are as follows for Figure 4 .2 .
Vi
= V CC ~ V BE “ I 3 R 3
(4.15)
i 2 r 2
= V BE + I 3 R 3
(4.16)
= h-h
(4.17)
E b
= R-iRg/CR-J+Rr,)
(4.18)
V6
* Y CC “ V CE ~ I 3 E 3
(4.19)
V B
Eg ! | A E^ __ TT
“ (Eg )! pR^) + E^ X GC
(4.20)
34
let
V BE = °* 5 v
V CE = 2.25 7
Iq = 0,6 mA
and R^ = 1 .5 K-ohms
Then from equation (4.19)
and therefore
From equation (4.15)
and from equation (4.16)
IgRg = 2.85 volts,
Eg 4.7 K-ohms .
I-jE-j =4.6 volts
I 2 R 2 = 1 .4 volts.
For a stability factor of 10, Eg may be chosen as
13.5 K-ohms and then the values of R-j and R 2 may be
calculated .
Neglecting the value of Ig in comparison with 1^
and I 2 , we get,
W^Rq = R l / S 2 = 4.6/1 .4 - 3.3
i.e . R-j = 3.3 R 2 (4,21 )
From equations (4.1 8) and (4.21) we find
R-j =56 K-ohms, R 2 = 17 K-ohms
So, the design - values of the bias resistors are as follows,
R-j =51 K— ohms, R^ = 1.5 K-ohms
R 2 = 15 K-ohms R 4 = 4.7 K-ohms
and also V-g = 1 .2 volts approximately .
35
As mentioned in previous section the voltage gain
of all the three stages has been calculated in Appendix 'A 1
by the approximate ’h 1 parameters of a typical low frequency,
small signal transistor .
Approximate values for gains of these two R-G
coupled stages may be calculated as follows.
Stage I
Rg = 4.7 K-ohms
and the input impedance (^j_ n 2 ^ "the next common emitter
stage may be taken as 2 K-ohms then, R^ for the first stage
is given by
E I = E 6 II S in 2 = 1 •+ K - ohms
Stage II
r 6 = 4.7 K-ohms
and the input impedance of the low pass filter along with
may be taken as (R iri ^ = 50 K-ohms).
R^ for the second stage = Rg j R ^ ^ =4*? K-ohms
Therefore G Tr = 1 * 7 .
v 2
36
How, we know the approximate values of & Y ^ , G and the
common collector voltage gain (approximately equal to
unity). Therefore, the overall voltage gain of the three
stages including the p re -amplifier is
G = G ,G .1 - approximately .
\ 2
Then, the gain is adjusted by the potentiometer shown in
Figure 4.1.
The input resistance of common emitter stages is
low (generally below 5 K-ohms), large coupling capacitors
C c are used (such as 10/uF). This helps in improving low
frequency response of the amplifier. The bypass capacitor CH
in Figure 4.2 governs the low frequency response and gives
7
a value for lower 3 db cutoff point by the formula
(/3+1 )R e + R ± +
f 3db = T^s^prs^r
( 4 . 22 )
’where
Rip - parallel combination of R , R Q (the output
resistance of the transistor) R & and R^ in
bias circuit and Rp (the input resistance of
the transistor).
From this we find that f_ ,,
odb
20 Hz
3
Similarly, lower 3db cutoff may also be calculated for
Rq. is the source resistance.
f 3db = (V E i )/(2TLC G( R 3 E i +VV E G E i»
(4.23)
= 50 Hz
37
A low pass filter is connected at the output of the
amplifier stages, so that audio can go to the modulator, but
r.f. can not come to these audio stages. This is simply a
i?i-section L.C. filter with the values of 1 and 0 so that
the shunt branch C offers minimum impedance for high fre-
quencies and high impedance for low frequencies and the
scries branch L offers minimum impedance for low frequencies
and high impedance for high frequencies. The values of 1 and
C are
I = 1.5 mH, C = 0.003 /UP
The filter is shown in figure 4.3.
4.5 Design of Osciflator-cum-llodulator
The oscillator designed is Hartley type^. Transistor
CH 911 is used as the active device for this circuit. This
gives good performance at desired frequency of 1 .3 MHz ,
because its ^ = 350 MHz. The emitter-base junction is
forward biased with a (-6 volts) battery and the collector
base junction is reverse biased with a (+6 volts) battery
through the tank circuit coil.
Current in the emitter is kept very low so that
the circuit gives oscillations of very low amplitude.
I-g = 0.125 mil.
Therefore, the value of emitter resistance is
E-j = 6/0.125 = 47 K-ohms approximately.
C^, and Cg are the bypass capacitors, that bypass all the
38
r .f » whatever comes, so that it does not go into the
battery .
The impedance of the capacitors is kept to be very
low as compared to the parallel impedance that is going to
the supply (i.e. approximately one tenth or even lower)
C 3 = 0 5 = C g = 0.01 yuF
The value of feedback capacitor G-j and the tapping
in the t uhk coil of the oscillator (for feedback) are chosen
experimentally to give stable and sufficient amount of
feedback so that the circuit oscillates at stable frequency.
R.xP. Choke and L-j , L* are chosen so that they block
the r.f. signal at 1.3 MHz and do not allow even a very small
amount of signal through them.
L-j =2.0 mH, L^ = 1 .5 mH.
1-j resonates exactly at 1 .3 MHz, with its self -capacitance
and blocks the signal to go to the other side .
The tank circuit capacitance C 2 and inductance L 2
are designed such that they exactly resonate at 1 .5 MHz
when a reverse bias voltage of 1 .8 volts (fixed) is applied
to the diode D-j in the modulator circuit.
Let
1 2 = 20/UH and f = 1 .3 MHz
then C 2 = 749 pL
Capacitance is designed in a way,' so that, it does
not effect the tank circuit capacitance appreciably and the
variations of the junction capacitance of the diode with
tho variations in reverse bias on its junction. The
suitable value found is
c 4 = 100 pF
because, the junction capacitance of the diode varies in
the range of 30 pF approximately.
Diode D^ is biased at 1 .8 volts reverse bias from
a (-6 volts) battery. Voltage across the diode 'V^ 1
(Figure 4.4) is
V d = 6 x R 3 /(R 2 +H 3 ) (4.24)
Values of R 2 and R 3 are chosen which do not load the
oscillator tank circuit and give proper value of bias.
let
R 3 = 75 E-ohms
and then from equation (4.24) R 2 = 180 K-ohms .
Diode CD -21 is used in the modulator tank circuit
as discussed in previous chapter.
4.6 Design of R.F. Amplifiers
In the last section oscillator has been designed
for low output voltage level, such that it does not have
any adverse effect on the modulator circuit due to high
amplitude of oscillations. Now since frequency is to
be multiplied, the signal is to be fed to the class f C f
amplifiers (operating in the nonlinear range of the
transistor) tuned to the harmonics of the input, we need
40
-67 -67
E-j =47 K-ohms
Rg = 130 K-ohms
R* = 75 K-ohms
R^ as 100 ohms decoupling resistor
1-j ss R.F . Choke at 1*3 MHz approximately
Jig — lank circuit inductance = 20 ytiH approximately
Lj = k.P, Choke at 1.3 MHz approximately
C-j =s Feedback capacitor 1,000 pF
Cg = Tank circuit capacitance = ^49 pF approximately
C^ = Bypass capacitor 0*01 yuF
C^ = Coupling capacitor 100 pF
C^ = Bypass capacitor 0,01 yuF
Cg = Bypass capacitor 0.01 yuF
I 1 = CH-91 1 (ffiO
D 1 * CD-21
Figure 4.4: Osc Hlator-cum-ModuLator Circuit.
41
a higher voltage than the one that is obtained from the
output of the oscillator and therefore, r.f. amplifier in
between the oscillator and multiplier stages.
Similarly, the r.f. amplifier is also needed when
the signal at the output of the last multiplier stage is
very small and it is desired to transmit it to a required
distance. It is not necessary that the r.f. amplifiers
operate in the linear range of the transistor, The r.f,
amplifiers operate in class ’O' condition to give better
efficiency .
From Figure 4.5, E-j is chosen such that a desired
current is passed through the transistor, let the emitter
current isl'2 mil then a value of Ej =5 .1 K-ohms will be
alright for this. A (+ 6 volts) battery Is used to bias
the collector in reverse bias. She tuned circuit design
procedure is the same as followed for oscillator,
Table 4.1 gives the values of frequency, inductance
and capacitance in the tank circuit.
As shown in Figure 4.5, variable capacitance is
used in the tuned circuit to tune the tank circuit to
the desired frequency.
At the end to get more power class 'C 1 r.f, stage
Is used. Its design is not at all different then the design
of the last frequency multiplier stage except that only one
tank circuit is used instead of two and also the neutralising
circuit is not used*
42
+6V
R-j =5.1 K-pinas
= Secondary of the input transformer
I <2 = Tank circuit indue tanee
L 3 = R.F. Choke
C-j = Bypass capacitor 0.01 /uF
C 2 = Tank circuit capacitance
= Bypass capacitor 0.01 /Up
T-j = C IB-911 (HPH)
Figure 4.5: R.F. acplifier.
43
4 .7 De sign of Frequency Multiplier Stages
1'here is not much of difference in the design of
frequency multipliers that have been incorporated in the
R ,3? , amplifiers except that the multiplier is operated
in class 1 C 1 condition to give a waveform (output) less
than half a cycle and the transistor is biased beyond the
cutoff point of the transistor and the output tank is
tuned to the harmonics of the input frequency. Collector
base junction is also biased in the same way as done in
r.f. amplifiers.
She value of the tank circuit components (induc-
tance and capacitance ) are given in fable 4.2. In the
case of last multiplier stage neutralising is also
employed as shown in the overall circuit diagram.
Design of frequency multipliers is not much
involved, the only thing very important is the design of
coils and transformers that are being used at the input
and output of the circuit and due consideration is given
to their design in the next section.
In the output tank there are two tank circuits
used, employing a potential devider type of arrangement
the capacitance is chosen such that it gives compara-
tively less admittance at the working frequency than the
tank circuit .
The attenuator provided by the capacitor 0^ and
the tank circuit prevents loadirg of the Q of the overall
circuit.
44
- Secondary of the input transformer
I>2 ~ Primary of the output transformer
- Inductance of the tank circuit
C-j j ^2 - Capacitance of the tank circuit
C^ - Potential divider capacitance
C 4 ,C 5 - Bypass capacitors
S-j ~ Decoupling resistors
T 1 — GIL-91 1 (mi)
Figure 4.6: Frequency multiplier.
45
Table 4.1
Tuned circuit inductances and capacitances for R.F.
amplifiers .
No.
Frequency
Inductance
Capacitance
MHz
pm.
pF
1
1.5
20
749
2
70.2
0.4
13
Table 4.2
Tuned circuit inductances and capacitances for
frequency multipliers.
No.
Fre quency
Inductance
/m
Capacitance
Input
MHz
Multiplying
factor
Output
MHz
1
1 .3
x3
3*9
16.7
100
2
3.9
x3
11 .7
2.0
93
3
11.7
x3
35.1
0.5
41
4
35.1
x2
70.2
0.4
13
46
4.8 Design of C oils and Tr ansformers
Dor the frequency range, that has been taken into
account in this project the coils designed are all single
layer solenoid type. Dor different frequencies, different
gauge of wire has been used to give minimum losses, and a
high Q and therefore a good selectivity. All the coils,
including at high frequency are wound on formers in side
which there is no core, because at these frequencies the
losses are high which is undesirable.
The design of high frequency coils depends more
on practice and experience, then on theory. Dor the
designing of inductors at high frequency lots of empirical
formulas are available in the design handbooks . However
the following empirical formulae is taken into account for
calculations and design of the coil.
Dor a single layer solenoid: 10
Inductance L = K (4.25)
where, n = Ho < of turns in the coil
a = Radius of the coil measured from the
axis to the centre of the wire,
b = Length of the coil, and
K as f (2a/b) from the table s given in books,
referred at the end in Bibliography.
Knowing the value of K from the table and taking
all other factors into account approximate calculations were
made. It is not worthwhile to give all details about the
calculations in this report.
47
In the case of this circuit,
value of 1 a ' = 0.4 cm + radius of the wire
because the outer radius of the former is 0.4 cm.
The detailed data about different coils that are
used in the circuit is given in figure 4,7 , and the value of
the tank circuit induct .nccs and capacitances have <ncn put
together for different circuits from lahLe 4.1 and Table 4,2
in the Table 4.3 for easy references.
from figure 4.7, it is found that at some places
transformer has been used for coupling to the next stage
and at some, places tapping is done in the primary coil
itself. T hi s is all because of practical convenience in the
design and working.
The number of turns in the secondary winding are
decided, having in mind the impedance matching from first
stage to the next one. following approximate data have
been taken into account for the same.
Tank circuit impedance = 20 K-ohms approximately
Common emitter input impedance = 2 K-ohms
approximately.
Cascading of CE to CE Configuration:
Input impedance = 2 K-ohms
Output impedance Z Q = 20 K-ohms
z 0 /Z ± = 20/2 = (HyUg) 2
Therefore, K-j/Kg = 3 approximately,
where K-j and 1 2 are 'the number of turns in primary and
secondary of the transformer respectively.
48
(a) Oscillator Coil
(Wire Gauge 34SWG)
(b) R.F .Amplifier Coil
(Wire Gauge 34SWG)
IT i Ij 1 Q-j | I ^ 2 ^
i_ B 1 — i
(c) First Frequency
Multiplier Coil
(Wire Gauge 28SWG)
r~
1T 1?1 a 1
No.
IT"
I(/UH)' "
Q
1
70
20
105
2
22
4
85
3
16
2.5
60
1
70
20
105
2
16
2.5
60
1
52
16.7 115
2
12
1 .9 80
(d) Second Frequency
- • Multiplier Coil
(Wire Gauge 28SWG)
r ~
KT-jL-j
u
( e ) Third Fre que ncy
1ST.
I^X.%
[Multiplier coll
1 (Wire Gauge 20SWG)
(f ) f Forth Fr equency
B Multiplier and
-5 T? ^ -Powpp AttoI i
hhSi.
R.F. Power Amplifier
Coils(Wire Guage
18SWG) .
1
2
1
1
15
6
8
4
2.0 110
0.3 95
0.5 125
0.4 150
1 - Number of turns, 1 - Inductance, Q. - Quality factor
of the coil.
Figure 4.7s Coil Data.
'Table 4.3
Tuned circuit inductances and capacitances for different
tank circuits
No.
Circuit type
Frequency
MHz
Induc-
tance
/UH
Cap aci-
tance
pF
1
Oscillator
1 .3
20
749
2
R.F, amplifier
1 .3
20
749
3
First frequency multipli
.er 3.9
16.7
100
4
Second frequency
-
multiplier
11 .7
o
•
CM
93
5
Third frequency
multiplier
35.1
0,5
41
6
Forth frequency
multiplier
70.2
0.4
13
7
R .F .power amplifier
70.2
0.4
13
In some cases it has not been praetic;
- uJ-'-aUJ.ti b O ug v
the same turns ratio as desired above due to practical
reasons such as when already lass number of turns are
chere in the primary.
Qyerall Circuit I>: ag ^am
ke overall circuit diagram is shown in Figure 4 8
thS ValUSS ° f 1 6 brents are also given neV
Jhe components. Different blocks have been specified with
eir names, operations and operating frequencies, different
stages are coupled either by B-0 coupli^ or by transformer
or auto-transformer type of coupling. This circuit diagram
°7 ^ °° MParea tD the S " ic Wool: diagram and audio am
radio stages may be distinguished.
■AS®, £*i
Input from
the micro -
12 §1
H5 1.55
L+: I 3000 X 7C
4-Tr
✓dvro tlio
\X)bollector
of oscil-
lator
Audio amplifier stages
■ LP Modula--
f alter tor
circuit
Osc illator
1 .3MEz
-BP Amplifier — 4* S' irst Frequency
i rz -nrorr , mulTiplier
.3 L^z 3.9MHz
4
locf X
1 r
10
1 y ^ 100 ji
-6V +6V -6V
_J W IJ
i 100 1 lioof-
100 1 x |i j-
+6V -67 +67
Second Frequency — »L- ^ird f re quencxJ^^Pre quenc^ .
multiplier * multiplier “ mu Ji 1 Hra ; ’’ ^ t
1 1 ,7MHz 35.1 Tffiz er 70.215Hz power _
9 • <r>4 rvvn *1 -4 -P *v-k
11.7KHZ 35.1 MHz er. ru.^mz power
•' amplifier
_ 70.2 MHz
Decoupling Resistors are in ohms and rest in K-ohms.
Primmer capacitors are 4-70 pP-and all other to lues are given
in the text.
Figure 4.8: Overall Circuit diagram of the transmitter
at 70.2 MHz.
CHAPQER 7
RESULTS
5.1 Carrier Frequency and Frequency Stability
Following are the measurements Knaie and the results
of them on frequency stability.
Carrier frequency of the transmitter = 70.2 MHz approx.
Frequency stability of the carrier = +0.5 KHz approx.
All these measurements are done at the starting
frequency of the transmitter and then multiplied by the
proper factor. A Decade counter was used to make these
measurements which goes up to 100 MHz with the plug-in- uni t
used. 'The reason for making these measurements at low
frequency is that, that at high frequency the input
capacitance and all other factors of the counter also
come into picture thereby reducing the amplitude of the
waveform and decreasing the frequency. Therefore, the
measurement of frequency and its stability were done at
starting point (oscillator frequency). Also the measurement
of frequency deviation that are shown in the next section
were done at this frequency only.
5 .2 Freq uency Deviation
The measurements waste for frequency deviation at
oscillator frequency itself are given in Table 5.1. From
this table we can find out the deviation needed and adjust
the audio signal accordingly such that we get +75 KHz,
frequency deviation at centre frequency of 70 1,5Hz, The
graph of this has been plotted in Figures 5.1 and 5.2.
5 .3 Tower Output
The required power output is actually one watt, but
with the Indian transistors available, at present time
(at this high frequency) this much of power cannot be
attained and hence the power that is available from the
transmitter is only a few tens of milliwatts.
In Appendix B a few calculations have been carried
out using a formulae for transmitted power. There it has
been assumed that the transmitter transmits only to area
of 2 km radius around it .
As and when Indian transistors at high frequency
and high power level are available, the power requirement
may be fulfilled by using a power amplifier (push-pull).
From the measurements output voltage at the
vertical aerial of a length of approximately equal to
quarter wavelength is 3.0 volts peak to peak which canes
out to be approximately 1 volt r.m.s. Therefore, the
power transmitted from the antenna is approximately given
Table 5 .1
Resu l ts of Rreguency Measurements
54
!To.
Reverse bias
voltage in
volts
Junction
capacitance
in pH
Rre quency
in
KHz
1
1 .1
34.3
.1297.000
2
1 .2
33.5
1297.400
3
1.3
32.8
1297.800
4
1 .4
32.2
1298.200
5
1 .5
31 .7
1298.600
6
1 .6
31 .05
1299.000
7
1 .7
30.6
1299.500
8
1 .8
30.0
1300.000
9
1 .9
29.6
1300.400
10
2.0
29.2
1300.900
11
2.1
28.75
1301 .300
12
2.2
28.38
1301 .700
13
2.3
28.02
1302.050
14
2.4
27.60
1302.400
15
2.5
27.25
1302.800
Reverse bias
in volts
Pigure 5.1s Junction capacitance vs, reverse bias
voltage on the diode.
56
figure 5.2: Oscillator frequency vs.
bias voltage on the diode
reverse
by 1/H, where R is the radiation resistance of the antenna,
let it be 20 ohms for a quarter wave antenna then the power
transmitted is 50 mW approximately which is sufficient for
transmitting the signal for a distance of 2 km (Appendix B)
CEAPOSER VI
C OITCLUS IOII
The work carried out is not now but the ingenuity
of the work is that, all the components that have been
made use of in the circuits are indigenous.
Since variable capacitance diodes of Indian make
are not freely available in the market. A simple Indian
diode (junction diode) ’CD-21 ’ from "Continental Devices"
Faridabad, has been used to perform the functions of a
varicap.
Ihe original required power of 1W could not be
achieved because high frequency and high power transistors
that are needed to give 1 Yf power are not available in the
Ind ian market .
In the modulation circuit a fixed reverse bias
to the diode (from a -6V battery through a potential
divider arrangement) is given, which may not be suitable,
because if the battery voltage drops down, the centre
carrier frequency will also charge. If a zener diode of
suitable value is available, that can be put in this biasing
circuit to get rid of this problem, then no other modifi-
cation will be necessary.
Finally, a frequency of approximately 70.2 MHz
has been attained and a frequency deviation of +75 KHz
by adjusting the audio signal level..
APPEEDUX-A
G-AUf OP CASCADED AUDIO AMPLIFIERS
Here the voltage gain has been calculated for the
three stage amplifier using transistor of a typical type..’
Pirst of them is a common collector configuration with an
unbypassed emitter resistance and the next two are common
emitter stages .
Ihe formulae for composite ! h’ parameters for two
11 ^ "
cascaded stages are given below
A 2 ^1
h.
11
h 11 -
hi
1+1^2 H^j
h.
11
(A1 , 1 )
(A1
o N
(A1 .3)
(A1 .4)
where
h
h.
h
'nn
T
inn
n
■“urn
1 h’ parameters of the two cascaded stages
l h' parameters of the first stage
'hi parameters of the second stage.
For a
impedance is
given below 12
cODEon collector stage where the emitter load
Uhbypassed the modified >h> paraneters are
h 1 1 ~ h 11 + (1+hgi )Z q
(41 .5)
h 12 = h 12 ^22 Z e
(41 .6)
h 21 ~ ^21 approximately
Ul .7)
h 22 = h 22 approximately
(41 .8)
where
an ' modified
parameters
h wi ~ Parameters of a common
Z e - enltter load iapedance
collector stage
For a typical small
amplifier transistor, *h r
below:
signal, audio frequency
parameters may be taken as
^ 2
h 21
^22
S
where S
Co mmon emitter
1 ,800 ohms
750x1 0~ 6
49
25 /Umhos
0.81 6
Co mmon collector
1 ,800 ohms
1
-50
25/hmhos
- 1,110
- h l2 h2i/h 11 h 22 .
61
Now, from equations (A1 .5) to (A1 .8) parameters for a
common collector stage with an unbypassed emitter load
impedance (1 IC-ohm approximately) may be modified and then
using equations (A1 .1 ) to (A1 .4) the ’h* parameters of the
three stages cascaded together (CC-CE-CB) are calculated
taking two stages at a tine and we get the following
results for all the three stage 'h l parameters.
Parame
ters CE
cc
CO with
emitter
load
CC with
emitter
load &
CE
CC with
emitter
load &
CE-CE
1
1 .8
1.8
47.2
49.35
49.35 Koh]
^ 2
750x1 0" 6
1
25x1 0 -3
22.7x1 0" 6
0.01 7x1 0“ 6
hgi
49
-50
-50
23.4
1,095
h 22
25
25
25
25
2^4mhos
S
0.816
-1,110
1 .06
0.431x10"^
-1 2.6x1 0“ 6
Now, the voltage gain is given by
(A1.9)
Lettirg the value of (load impedance) to be 4.3 K-ohms
the gain comes out to be 4,250.
APPEKDIX-B
CAIiCULAPIOE OP SEQUIBED POWER
Pile formula for Pield Intens
is given by
* ~ d
(A2 * 1 )
for a vertical aerial.
Where, P - Pield Intensity in volts/meter
P - PoY/er required in watts
d - Distance between the transmitter and
the receiver in meters.
Hence, for our calculations we take the following data
into account.
P = 500yu volts/meter
d = 2,000 meters
How, from equation (A2.1)
(A2.2)
Prom this the power required comes out to be approximately
20 mW
B 131 I OGRAPHY
1. Panter, P.P., "Modulation, noise and spectral analysis"
H.Y. McGraw-Hill, 1965, pp .39 1-393.
2. SYIVAHIA, "Varactor Handbook".
3-4 .Continental Devices, Paridabad, "Data Manual".
5. Hunter, L.P., "Handbook of semiconductor electronics",
H.Y., McGraw-Hill, 1962, p.11-26.
6. Hunter, I.P., "Handbook of semiconductor electronics",
D.Y . , McGraw-Hill, 1 9 62, p. 11-92.
7-8.Pitchen, P.G., "transistor circuit analysis and design"
D Van Hostrand Company, Inc. H.Y., i960, p.121.
9. "400 Ideas for design" (selected from"electronic
design"), IT.Y., Heyden Book Co., 1964, p.193.
10. Henny, K., "Electronic Components handbook", IT.Y.,
McGraw-Hill, 1957, p.3-15.
11. Hunter, L.P., "Handbook of semiconductor electronics",
H.Y., McGraw-Hill, 1962, p. 11-29.
12. Hunter, B.P., "Handbook of semiconductor electronics"',
M.Y. , HcGraw-Hill , 1 9 62 , p . 1 1 -3 1 .
13. Sjobbema, D.J.W., "Aerials", Philips Paperbacks,
1964, p.15.
1 I. !. T, KANPUR 7 I
I g} gN ”t <■ ' A. u UBSARY, f