Document text
UNCLASSIFIED
AD NUMBER
AD801769
NEW LIMITATION CHANGE
TO
Approved for public release, distribution
unlimited
FROM
Distribution: No foreign.
AUTHORITY
SAMSO, USAF ltr . , 28 Feb 1972
THIS PAGE IS UNCLASSIFIED
fl-D 80/ 7 6?
PAM-FM GROUND STATION
(G-A AND VIBRATION)
VOLUME !!
THEORY OF OPERATION AND MAINTENANCE
(FIRST REVISION)
LMSD-288025
UUwW'— •-* - -
CL,
23 FEBRUARY 1960
REVISED 1 SEPTEMBER 1960
r /) ,,
CONTRACT AF©4(647)-347
This document i* subject t©
speciai export controls and
each transmittal to foreign
nationals may be made only
with prior approval of
MISSILES and SPACE DIVISION
mrn
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I :
timi 1 A L
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L.OCKHEEE1 AIRCRAFT C O F! F O R A T I O N
• U N N YVALE, CALIF.
NOTICE
The information and design disclose i herein were originated
by and are the property of Lockheed Aircraft Corporation.
Lockheed reserves all patent, proprietary, design, manufac¬
turing, reproduction, use, and sales rights tkoreto, and to
any article disc*, used hen in, except to the extent rights are
expressly granted to others. The foregoing does not apply to
vendor proprietary parts.
■‘in— r wrisiiid— mi— ni-iMi— — i«.e«aari,i.ag
This Instruction manual on the PAM-FM Ground Station has been prepared as a guide
to the operation and maintenance of the Vibration and G-A Ground Station developed
under Contract AF 04(847)-347. It Is divided into two volumes: Vol. I. Installation;
Checkout, and Operation: Vol. CL Theory of Operation and Maintenance.
Volume I is published In two parts. Part 1 describes the Installation, checkout, and
operation procedures for the trailer-mounted station at Atlantic Missile Range
(Patrick Air Force Base). Part 2 describes the installation, checkout, and operation
procedures applicable at locations where the ground station is installed on a perma¬
nent or semi-permanent basis. Part 2 constitutes a manual of instruction for a com¬
plete ground station with record, reproduce, and display capabilities for Vibration
and G-A signals. Operators can use the instructions that apply to their installation
»Hp£UJuiUv5 ixii'j ms Uu i-iOuS that do not anpty, Thun. If ctp—sllitict at a
specific installation should change, appropriate instructions for installation, check¬
out, and operation will be available.
Volume n, published as a single unit, contains a description of the theory of operation
for a ground station having record and reproduce capabilities for Vibration and Q-A
and specific information designed to assist the operator in maintenance of the
equipment.
Instruction manuals for operation and maintenance of components supplied by manu¬
facturers other than Lockheed Missiles and Space Division are also furnished to each
station .
LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
LMSD-288025
CONTENTS
Section
NOTICE
FOREWORD
LIST OF ILLUSTRATIONS
7 . THEORY OF OPERATION
Introduction
7.1.1
Vibration
7.1.2
G-A
Vibration
7.2.1
Receiver
7.2.2
Base Band Unit, Record Mode
7. 2. 2.1
DC Amplifier
7.2. 2.2
Noise Filter
7. 2. 2.3
Noise Filter Amplifier
7.2. 2.4
Reference Voltage Optional Clamp
7. 2. 2. 5
Gate Driver Amplifier
7. 2. 2. 3
Reference Amplifier
7.2.3
Demultiplexer, Record Mode
7. 2. 3.1
Data Sync Separator
7 0 Q 0
. • «C. J • —
Frame Sync Separator
7. 2.3.3
Eight-Bit shift Register
7. 2.3.4
Programmer
7. 2. 3. 5
Sync Selector
7. 2. 3. 6
Sync Gate
7. 2. 3. 7
Zero Data Selector
Page
ill
v
xiil
7~1
7-1
7-2
7-7
7-11
7-11
7-11
7-17
7-18
7-20
7-21
7-22
7-23
7-2#
7-28
7-30
7-31
7-31
7-33
7-34
vil
LOCKHEED AIRCRAFT CORPORATION
MISSILES end SPACE DIVISION
LMSD- 288025
Section
7.3
Pag>»
7. 2, 3. 8
Frequency Divider
7-35
7. 2.3.9
Eight-Channel Pulse Sequence r
7-36
*t OQ
7. 2. 3. 11
Data Sync Delay Record
7-37
7.2.4
Output Filters and Amplifiers
7-38
7.2.5
Visual Display Unit
7-40
7.2.6
Analog-to-Dlgttal Converter
7-40
7.2.7
Digital Record Electronics
7-46
7. 2.7. 1
Frame Sync Storage Record
7-48
7. 2.7. 2
Pulse Amplifier
7-49
7. 2.7.3
Digital Record Amplifier
7-49
7.2.8
Magnetic Tape Recorder
7-51
7.2.9
Digital Reproduce Electronics
7-52
7. 2.9.1
Digital Reproduce Amplifier
7-54
7. 2.9.2
Data Storage and Gate
7-55
7. 2.9.3
Data Sync Delay Reproduce
7-57
7. 2.9.4
Delay Command Pulse
7-57
7.2.10
Digital -to -Analog Converter
7-58
7.2.11
Base Band Unit, Reproduce Mode
7-59
7.2.12
Demultiplexer, Reproduce Mode
7-59
7.2. 12. 1
Duty Cycle I
7-59
7.2.12.2
Frame Sync Delay Reproduce
7-63
7.2.13
Power Supply Interlock
7-64
7.2.14
Relay Board
7-64
7 g 2: 15
iviMiii mOmiui raum
n
i -uu
7.2.16
Signal Strength and Voice Record and Reproduce
Filters
7-65
Q-A
7-67
FV O 1
- ♦ O. A
UC *
7 - n 7
viii
■*D AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
JUlUOi/‘’&OOV4il
Section
Page
7.n. 2
Bane Band Unit. Record Mode
7-67
7 3 2 1
nr. AmrsMflor
- - n - 1 - - -
7-71
7. 3. 2. 2
Noise Filter
7-73
7. 3. 2. 3
Noiec Filter Amplifier
7-74
7. 3. 2. 4
Reference Voltage Optional Clamp
7-76
7. 3. 2. 5
Gate Driver Amplifier
7-77
7. 3.2.6
Reference Amplifier
7-78
7.3.3
Demultiplexer, Record Mode
7-79
7.3.3. 1
Data Sync Separator
7-82
7. 3. 3. 2
Frame Sync Separator
7-85
7. 3. 3. 3
Eight-Bit Shift Register
7-86
7. 3, 3. 4
One-Bit Shift Register
7-87
7. 3. 3. 5
Sync Selector
7-89
7. 3.3. 6
Sync Gate
7-90
7. 3. 3. 7
Frequency Divider
7-92
7. 3. 3. 8
Eight-Channel Pulse Sequencer
7-92
7. 3. 3. 9
Matrix
7-93
7.3.3. 10
Data Gates
rr nn
< “OO
7.3.3.11
Pulse Set
7-94
7.3.3.12
Duty Cycle II
7-96
7 o >1 i o
1 ; li . U i ■ a
Data Sync Delay Record
7-96
7.. 3.14
DC Reference Filter
7-97
1 . O • **
Sample and Hold Output Circuits
7-98
7.3.4. 1
Sample and Hold
“_!£./}
7. 3. 4. 2
Plus/Minus 10— Volt Regulator
7 101
7.3.5
Analog-to-Dlgital Converter
7-102
7.3.6
Digital Record Electronics
7-107
7. 3. 6.1
Frame Sync Storage Record
7-107
7. 3. 6. 2
Pulse Amplifier
7-108
7. 3. 6. 3
Digital Record Amplifier
7-109
lx
LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
LMSD -288025
Section
Page
8.
7.3.7
Magnetic Tape Recorder
rt i i a
1 ' A A VP
7.3.8
Digital Reproduce Electronics
7-112
7.3.8. 1
Digital Reproduce Amplifier
7-112
7. 3.8.2
Data Storage and Gate
7-114
7. 3. 8. 3
Data Synr Delay Reproduce
7-115
7. 3. 8. 4
Delay Command Pulse
7-116
7-3 9
Digital -to-Analog Converter
7-117
7.3. 10
Baer Band Unit, Reproduce Mode
7-117
7.3.11
Demultiplexer, Reproduce Mode
7-117
'..3.11.1
Frame Sync Delay Reproduce
7-120
7.3.12
Power Supply Interlock
7-121
7.3. 13
Test Signal Generator
7-121
7.3.14
Relay Board
7-122
7.3.15
Main Monitor Panel
7-123
7.3.16
Signal Strength and Voice Record and
Keprcuuce Filters
7-123
MAINTENANCE
8.1 Introduction
8-1
8.1.1
Scope
8-1
8.1.2
General Information
8-2
8.2 General Instruction#
8-3
8.3 Troubleshooting for Absent or Incorrect Inputs
8-4
8.4 Troubleshooting Blocking Oscillators. Gan -Shots,
and Flip-Flops 8-5
8.4.1
Blocking Oscillator
8*5
8.4.2
One-Shot
8-6
8.4.3
Flip-Flop
8-6
8.5 Receiver
8-7
8.6 DC Amplifier
S-7
8.7 Noise Filter. Vibration
8-10
8. 8 Noise Filter, G-A
8-11
x
LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
Section
8.5 NuUe f'iiier Ampiiiier
6. 10 Reference Voltage Optional Clamp
8.11 Gate Driver Amplifier
8. 12 Reference Amplifier
8.13 Data Sync Separator
8. 14 Frame Sync Separator
8. 15 Eight-Bit Shift Register
8. 16 One-Bit Shift Register
8. 17 Programmer
8. 18 Sync Selector
8. 19 Sync Gate
8. 20 Zero Data Selector
8.21 Frequency Divider
8.22 Eight -Channel Pulse Sequencer
8.23 Matrix
8. 24 Data Gates
8. 25 Pulse Set
8 . 26 Duty Cycle II
8. 27 Data Sync Delay Record
8. 28 Filter Board
8. 29 Sample and Hoid
8.30 DC Reference Filter
8.31 Frame Sync Storage Record
8=32 Pulse Amplifier
8. 33 Digital Record Amplifier
8.34 Digital Reproduce Amplifier
8.35 Data Storage and Gate
8.35 Data Sync Delay Reproduce
8. 37 Delay Command Pulse
8. 38 Duty Cycle I
xi
tetesMM 1
i
LmSD-255025
Page
8-12
8-13
8-14
8-10
8-16
8-21
8-24
8-28
8-32
8-34
8-37
8-40
8-42
8-44
S 4C»
Vi -
8-50
8-55
8-58
8-60
8-61
8-61
8-63
8-67
5-69
8-70
8-73
8-76
8-78
8-80
8-82
I
B
»
m
I
I
8
P
LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
LMSD-288025
Section
Page
8.39 Frame Sync Delay Reproduce
8-84
8.40 Analog-to-Digital Converter
8-87
8.41 Magnetic Tape Reoordor
8-87
8.42 Power Supply Interlock
8-87
9.
VACUUM TUBE VOLTAGE CHART
9-1
10.
WIRING
10-1
11.
MONITOR SWITCH OUTPUTS
11-1
Appendix
SCHEMATICS, PARTS LISTS, AND COMPONENT ASSEMBLIES A-l
xil
frr' ilSrSiC? a -ri/^k i
rv i v.vKr *_*«•*. i « .
fe^4. .....
MISSILES and SPACE DIVISION
LMSD-288025
Liar Or I LLU btra xl ON S
Figure Page
7-1 Vibration PAM-FM Ground Station, Record Mode 7-8
7-2 Vibration PAM-FM Ground Station, Reproduce Mode 7-4
7-3 G-A PAM-FM Ground Station, Record Mode 7-8
7-4 G-A PAM-FM (Mound Station, Reproduce Mode 7-6
7-5 Typical Vibration PAM Rilse Train (Idealised) 7-8
7-6 Typical G-A PAM Pulse Train (Idealised) 7-10
7-7 Vibration Base Band Unit, Record Mode 7-13
7-8 Functional Diagram of Vibration Demultiplexer, Record Mode 7-24
7-8 Vibration Output Filters and Amplifiers 7-39
7-10 Analog -to-Digltal Conversion Process 7-44
7-11 Functional Diagram of Digital Record Electronics 7-47
7-12 Functional Diagram of Digital Reproduoe Electronics 7-63
7-13 Vibration Base Band Unit, Reproduce Mode 7-60
7-14 Functional Diagram of Vibration Demultiplexer, Reproduce Mode 7-61
7 -15 G-A Base Band Unit , Record Mode 7 -SS
7-16 Functional Diagram of G-A Demultiplexer, Record Mode 7-80
7-17 G-A Sample and Hold Output Circuits 7-99
7-18 G-A Base Band Unit, Reproduce Mode 7-118
7- 19 Functional Diagram of G-A Demultiplexer, Reproduce Mode 7-119
8- 1 Flip-Flop Convention 8-3
8-2 Base Band Unit Block Diagram (Sheet 1 of 2) 8-8
8-2 Base Band Unit Block Diagram (Sheet 2 of 2) 8-9
8-3 Data Sync Separator Block Diagram, Vibration 8-17
8-4 Data Sync Separator Block Diagram, G-A 8-18
8-5 Frame Sync Separator Block Diagram, Vibration 8-22
Revised 25 June 1960 xill
LOCKHEED AIRCRAFT CORFORATION
MISSILES and SPACE DIVISION
Figure
i-fl Frame Syne Separator Block Diagram, G-A
8-7 Elght-BU Shift Register Block Diagram, Vibration
8-8 Eight-Bit Shift Register Block Diagram, G-A
8-9 One -Bit Shift Register Block Diagram
8-10 Programmer Block Diagram
8-11 Sync Selector Block Diagram, Vibration
8-12 Sync Selector Block Diagram, G-A
8-13 Sync Gate Block Diagram
8-14 Zero Data Selector Block Diagram
8-15 Frequency Divider Block Diagram
8-16 Eight-Channel Pulse Sequencer Block Diagram
8-17 Matrix Block Diagram (Typical Element)
8-18 Data Gates Block Diagram
8-19 Pulse Set Block Diagram
8-20 Duty Cycle n Block Diagram
8-21 Data Sync Delay Record Block Diagram
8-22 Sample and Hold Block Diagram
8-23 DC Reference Filter Block Diagram
8-24 Frame Sync Storage Record Block Diagram
8-28 Pulse Amplifier Block Diagram
R-9A I Anmllflot* Ttlaimom
•» “ ■»* atvwva m ay i*
8-27 Digital Reproduce Amplifier Block Diagram
8-28 Data Storage and Gate Block Diagram
8-29 Data Sync Delay Reproduce Block Diagram
8-30 Delay Command Pulje Block Diagram
8-31 Duty Cycle I Block Diagram
8-32 Frame Sync Delay Reproduce Block Diagram
10-1 Base Band Unit Wiring Block Diagram
10-2 Vibration Demultiplexer Wiring Block Diagram -
Record and Reproduce
10-3 (Not used. Replaced by new Fig. 10-2, page 10-5. )
LM3D-28802-5
Page
8-23
8-25
8-26
8-29
8-33
8-35
8-36
8-38
8-41
8-43
8-45
8-49
8-51
8-56
8-58
8-60
8-62
8-64
8-68
8-69
O *71
u~| J.
8-74
8-77
8-79
8-81
8-83
8-85
1 A A
10-5
10-7
Revised 25 June 1960
xtv
LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
rwf ***
LMSD-28802E
1
i
1 1
F Inure
Page
f ’
10-4
G-A Demultiplexer Wiring Block Diagram
10-9
I;
10-5
Digital Record Electronics Wiring Block Diagram
10-11
10-8
Digital Reproduce Electronics W ir lng Block Dla^7am
10-13
i
A-l
Receiver Modifications
A-l
A-2
DC Amplifier
A-3
j ■
A-3
Noise Filter
A-5
A-4
Noise Filter Amplifier
A-7
1 :
A-5
Reference Voltage Optional Clamp
A-9
A-6
Gate Driver Amplifier
A-ll
i ■
L
A-7
Heference Amplifier (Sheet 1 of 3)
A-13
A-7
Reference Amplifier (Sheet 2 of 3)
A-15
A-7
Reference Amplifier (Sheet 3 of 3)
A-17
4
A-8
Data Sync Separator, Vibration
A-19
A-9
Frame Sync Separator, Vibration
A-21
T «
1
A-10
Eight-Bit Shift Register, Vibration
A- 23
A-ll
Programmer
A-26
r
u
.>-12
Sync Selector, Vibration
A-27
A-13
Sync Gate, Vibration
A-29
r
f
a-*
A-14
Zero Data Selector
A-31
A-15
Frequency Divider, Vibration
A -33
r
j
A-16
Eight -Channel Pulse Sequencer, Vibration
A-35
A- 17
Data Gates, Vibration
A-37
L*
A- 18
Data Sync Delay Record, Vibration
a asm
a -aw
ir
A- 19
Filter ^oard
a a »
A-*A
ir-
A-20
Datrac Modifications - Chassis One and Two
A-43
{ !
A-21
Datrac Modificatloi s - Chassis Three
A-45
1 ;
A-22
Datrae V. edifications - Chassis Nine
A-47
A- 23
Datrac External Modifications
A-49
j
A-24
Datrac Modifications - Record Outputs and Output Signal
Monitor Points
A-51
l
XV
LOCKHEED AIRCRAFT CORPORATION
MISSILES ood SPACE DfVISION
LMSD-288025
Figure
Page
A -OR
4T»~ *
VltatM.. OtmM OR-mm o Mum T1 aanuJ
« UJ IIV UU/1 H|C IWVUtU
A-53
A-26
Pulse Amplifier
A-55
A-27
Digital Record Amplifier
A-57
A-2S
Digital Reproduce Amplifier
A-59
A -29
Data Storage and Gate
A-61
A -30
Data Sync Delay Reproduce
A-63
A-31
Delay Command Pulse
A-65
A -32
Duty Cycle I
A-67
A-33
Frame Sync Delay Reproduce. Vibration
A-69
A-34
Power Supply Interlock £
A-71
A-35
Oa1«w
a r» rx
A“ « U
A-36
Monitor Panel
A-75
4-37
Signs! Strength and Voice Record and Reoroduce Filters
A-77
A-38
Data Sync Separator, G-A
A .70
41 1 o
A-39
Frame Sync Separator, G-A
A-81
A-40
Elght-Btt Shift Register, G-A
A -83
A- 41
One ' Bit Shift Register
A-85
A-42
Sync Select jr, G-A
A -87
A -43
Sync Gate, G-A
A-89
A -44
Frequency Divider, G-A
A-91
A -45
Eight-Channel Pulse Sequencer, G-A
A-93
A-46
Matrix
A-95
A -47
Data Gates, G-A
A-97
A -48
Pulse Set
A-99
A-49
Duty Cycle n
A-101
A -50
Data Sync Delay Record, G-A
A-103
A-51
DC Reference Filter
A-105
A-5 T
Sample and Hold
A-107
A-53
Plus/Minua 10-Volt Regulator
A-109
A-54
Frame Sync Delay Reproduce, G-A
A-lll
A-55
Test Signal Generator
A-113
xvi
LOCKHEED AIRCRAFT CORPORATION
MISSILES and SFACE DIVISION
IM8D- 288026
Section 7
THEORY OF OPERATION
7.1 INTRODUCTION
The purpose of the PAM-FM Ground Station is to receive, process, record, and
present for on-line, real-time readout PAM-FM telemetered information from a
vehicle. Certain Ground Station installations are capable of reproducing the recorded
information for delayed readout on visual-display equipment. The Ground Station con¬
sists of a Receiver, Base Band Unit, Demultiplexer, Digitizer (Datrac), Record and
Reproduce Electronics, a Magnetic Tape Recorder, Sample and Hold Output circuitry,
and in the case of Vibration operation, a Visual Display Unit (Vlsloorder).
The input to the receiver of the Ground Station la a PAM-FM signal. The receiver
output is an amplitude- modulated pulse train proportional to the pulse train delivered
to the vehicle transmitter by die vehicle multiplexer. This pulse train is amplified,
band-limited, and delivered to the Datrac for digitization. Each pulse of the pulse
train, including the sync intervals, is digitized into a nine-bit binary rord and de¬
livered to the Magnetic Tape Reoorder for parallel recording in Non-Return- to- Zero
(NRZ) form. The pulae train is also delivered to the Demultiplexer for separation
into individual channels corresponding to the channels of the vehicle multiplexer. The
information from the Demultiplexer Is used for real-time readout on visual display
equipment.
In the reproduce mode of operation, the recorded binary words are delivered to the
Datrac for conversion to analog form. This analog pulse train is delivered to the
Demultiplexer for separation into individual channels corresponding to the ohannels of
the vehicle multiplexer. The information from the Demultiplexer is then used for
delayed readout on visual display equipment. The Visual Display Unit (Vlsioorder)
7-1
».£ m!VS^<V(v
LOCKHEED AIRCRAFT CORPORATION
for Vibration is included certain 1 '«**ii«t,nnn r> n n»rt nf the* Ground station.
Visual display equipment for G-A la not lncl tded an a part of the Ground Station and
is not discussed in this manual. Block diagrams illustrating the signal flow in record
and reproduce modes of operation for the Vibration and G-A systems are phown in
Figs. 7-1, 7-k, 7-3, and 7-4.
Sinoe two data links. Vibration and G-A, are included in this Ground Station manual,
characteristics peculiar to each are described briefly in paragraphs 7. 1. 1 and 7. 1. 2.
The theory at operation for Vibration is described in detail in paragraph 7. and for
G-A In paragraph 7.3. Procedural instructions for maintenance are detailed in
Section 3.
7.1.1 Vibration
The Vibration data link is a PAM- FM communication system so arranged that it can
operate with a even high-frequency data channels with a bandwidth of 2600 cps each or
with six high~froqut'ncy data channels with a bandwidth of 2000 cps each and seven
subcommutated data channels with a bandwidth of 250 cps each. This system has a
sampling rate of 40,006 samples per second and a 50 percent duty cycle. In addition
to the data channels, there Is a subframe sync channel and an alternating frame sync.
This alternating frame sync channel provides additional reliability as well as zero
d&ts Tdibraie.
Cu«h j1 1 Is reserved for a main channel sync interval and a calibrate pulse. These
pulses appear on alternate frames. Channel B is subcommutated into eight channels.
Of these channels, 8. 1 la the subcommutated sync interval and Channels 8. 2 through
8.8 at . ubcommutated data channels. When subcommutated channels are not used,
Channel 8 operates as a high-frequency information channel without a sync interval.
With a basic clock rate of 40 kc, an Information pulse occurs every 25 microseconds.
A complete cycle, going through eight permutations of the subcommutated channel,
requires 1600 microseconds. During this 0.0016-seoond period, each subcommutated
7-2
LOCKHEED AliCRAFT CORPORATION
MISSILES and SPACF DIVISION
FIELD STRENGTH
L.MU>U-2liK0<Jb
LOCKHEED AIRCRAFT CORPORATION
MISSILES ond SPACE DIVISION
Fig. 7-3 <3-A PAM -FM Ground Station, Record Mode
CLEAR PULSE
1, MS n- 28 SO 2,1
9
i « tM^L' - Z
channel will produce one bit of information at a raie of 62:> samples i>er and
each high-frequency channel will produce eight b'fs of information at u rate of :>t)l)()
samples per second. There are eight information pulses tone frame) every 200
microseconds. Each main channel is equally spaced in time, and each sulx'ommutatcd
channel ia equally spaced In time.
A typical Vibration pulse tram (Fig, 7-5) has these characteristics with respect to
Demultiplexer input:
■ Refe once level of 0 volts (sync interval)
s Minimum uuia level ot i.o volts (corresponding to -2.5-volt input to
the vehicle multiplexer)
• Calibrate pulse level ol 4. 0 volts (corresponding to 0-volt input to the
veh ie 1 e muitiplexe r )
• Maximum data level of 0.5 volts (corresponding t> i2.5 volt input to
the vehicle multiplexer)
7.J.2 G-A
The G-A data link is a PAM-FM communication system arranged to have 29 channels
with a bandwidth of 200 cps each and seven channels with a bandwidth of 25 cps each.
Two additional 200-cps channels and an additional 25-cps channel are used tor
'^nchronization. This PAM information has a composite sampling rate of 16, 00C
samples per second and a 50-percent duty cycle. B.v the use of a subcommu fated
channel, the G-A system handles 36 channels of information. Of these, 29 are high-
frequency, or direct data channels, and seven are low-frequency, or subco.mnutated
data channels.
With the basic clock rate of 16 kc, an information pulse occurs every 62.5 micro¬
seconds. A complete cycle, going through the eight permutations of the subchannel,
requires 16, 000 microseconds. During this ;. 016- second period, each subcommutated
channel will produce one bit of information . the rate of 62.5 samples per second,
7-7
LOCKHEED AIRCRAFT CORPORATION
MISSILE! and SPACE DIVISION
LMSn-288025
and each high-frequency channel will produce eight bits of information at a rate of
500 samples per second. There are 32 information pulses (one frame) every 2000
microseconds. Each main channel is equally spaced in time, and each subcommutated
channel is equally spaced in time.
The 0- to 5-volt data is superimposed on a 1. 5-volt pedestal. Thus, the peak data
amplitude is approximately three-quarters of the peak PAM signal amplitude. Syn¬
chronization channels have no pedestal, but appear at the baseline level.
Channels 1 and 9 are reserved for main channel sync intervals. Channel 32 la sub¬
commutated into eight channels. Of these, Channel 32. 1 is the subcommutated ryoc
Interval and Channels 32. 2 through 32. 8 are subcommutated data channels.
The composite pulse train is bond-limited in the vehicle equipment to 35. 2 kc by a
single-pole filter and Is further band-limited on die ground (in the Noise Filter) fay
another single-pole filter with a cutoff frequency of 35. 2 kc.
A typical G-A composite pulse train (Fig. 7-6) has these characteristics with respect
to Demultiplexer input:
e Reference level of 0 volts (sync Interval)
e Minimum data level of 1. 5 volts (corresponding to 8-volt input to the
vehicle multiplexer)
• Maximum data level of 6. 5 volts (corresponding to a +5-volt Input to
the vehicle multiplexer)
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LOCKHEED AIRCRAFT CORPORATION
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LMSD-288 025
7.2 VIBRATION
7. 2. 1 Receiver
Input to the Vibration Ground Station la received at a modified Ne me -Clarke 1412
Telemetry Receiver as a PAM-FM signal. After the FM signal has been demodulated,
three signals are delivered to other equipment at the station. A de -coupled PAM sig¬
nal is delivered to the Base Band Unit at an average level of approximately +6 volts.
A field strength signal is delivered directly from the receiver to the FM electronics
of the Magnetic Tape Recorder for recording on analog track 14. An ac -coupled sig¬
nal, to be used as a backup for the digital recording, is delivered through an auxiliary
jack to the analog electronics of the Magnetic Tape Recorder for recording on analog
track 11. The modifications to the Nems-Clarke 1412 Telemetry Receiver provide a
dc -coupled output near ground potential and were made to achieve compatibility with
the PAM-FM Ground Station In the following manner:
e To provide dc -coupled and ac -coupled video with the phase opposite to
that provided by the unmodified receiver
e To provide video with a level Independent of any readily accessible
adjustment
This modification was accor ipllshed by bypassing the video amplifier and nleatntng an
output o i gwoi directly from csthodc ©» th? **
14«1aw /VIA 14
- rail \ V AV* fm
schematic diagram of the modifications is shown in Fig. A-l. Theory of operation
and operating and maintenance procedures are described in Instruction Manual for
Model 1412 Telemetry Receiver. Nems-Clarke, Inc. , Silver Spring, Maryland.
7. 2. 2 Base Band Unit, Record Mods
The purpose of the Base Band Unit is to
e Amplify the signal from the receiver and provide three separate output
signals, each of a different level and isolated from one another
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LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
LMSD-288025
• Insert correct d-c reference level Into two of the three output signals
m. limit *W fcmm ImlJA >1 llu Bill
.ImbaL
■ieWju>A > - a . . _ .a * - -
» tWVUV UiSl VMUV <41^
•Massive oros stalk
A block diagram of the Vibration Base Band Unit in the record mode is shown in
Fig. 7-7.
The three output signals of the Base Band Unit are (1) a 19-volt peak-to-peak signal
for the Analog-to-Digltsl Converter (Datrac), (2) a 7-volt peak-to-peak signal for the
Demultiplexer data gates, and (3) a 15-volt peak-to-peak signal for the Demultiplexer
sync circuits.
The 19-volt peak-to-peak signal for the Datrac must be referenced so that the mini¬
mum peak la -9. S volts. The 7-volt peak-to-peak signal for the data gates in refer¬
enced so that *aro output of the interpolation filters of the display circuitry corre¬
spond# to zero data, i.e., the minimum peak is approximately -1. 5 volts. The 15 -volt
peak-to-peak signal for the sync circuits is not referenced and is a -c coupled.
Since the Vibration PAM signal has a 40-kc pulse repetition rate, it must be considered
a high-speed system. Accuracy requirements approach two percent. The high repe¬
tition rate and accuracy requirements dictate the use of a finite memory type of filter.
Finite memory filters can be adjusted so that practically zero crosstalk is introduced
into the system. The filter Is adjusted so that the output reaches full amplitude of
the Input pulse during foe time of the pulse and decays to zero by the time the peak
value of foe succeeding pulse is reached. The accuracy of the adjustment determines
the amount of crosstalk introduced by the finite memory filter.
Two signals flow through the Base Band Unit. One la foe PAM pulse train, the other
ia the d-c reference feedback correction voltage that is derived from a portion of the
pulse train.
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LOCKHEED AIRCRAFT CORPORATION MISSILES and SPACE DIVISION
LM8D-288025
1W (tod from Am hmIii •*, «fc«eh i: approximately 1.4 volt# p##k-to-p««k in im-
pUMi, Mtora tbs DC Amplifier where it ia amplified approximately 10 times without
Mag Inverted. This amplifier Is composed of dirset-coupled circuits. A suitable
assess si srtbattlng positive Mas voltage from tbs receiver is included.
Tbs tsAifsk of tbs DC Amplifier, sow at a level of approximately 14 volts peak-to¬
psail, la fad into tbs Noise Filter described above. Here the slgnal-to-noise ratio of
the PAM pair train is Improved, and approximately 3 volts of negative offset voltage
are added to the output signal.
This signal is d»' -ored to the Noise Filter Amplifier at approximately 4 volts peak-
to-peak because of attenuation in the Noise Filter. The signal la then amplified so
that tbs Noise Filter Amplifier output to the Datrac la 19 volts peak-to-peak. An
adjustment called tbs Overall Cain la included in this amplifier to set the desired
level. An additional adjustment to correct the d-c level to -9 (t 0. 25) volts is also
Included in tbs Noise Filter Amplifier. This signal can be routed through the
Reference Voltar rJpti ' Cl* nap circuit if the Demultiplexer should fall to deliver
the correct d-c reference level voltage.
At this point the PAM pul '* train ia divided into three outputs. One output is the 19-
volt peak-to-peak signal . she Datrac, another is the 15-volt peak-to-peak signal to
the Demultiplexer sync circuits, and the third is the dc -coupled signal to the Gate
Driver Amplifier.
The Cate Driver Amplifier is used to attenuate the 19-volt peak-to-peak signal to a
7 -volt signal and supply a ivw source impedance to drive the data gates. A d-c offset
adjustment is Incorporated to adjust the minimum peak (sync interval) to approxi¬
mately -1. 5 volts. Incorporated in the Cate Driver Amplifier is a relay activated by
tbs Record-Reproduce switch in the Monitor Panel vo that the input to the data gates
by way of the Gats Driver Amplifier can be routed from the Datrac or the Noise Filter
Amplifier, depending on the mode of operation.
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The d-c reference correction voiiage originates in the Demultiplexer where the
calibrate puiae is sampled by the Zero Data Selector and smoothed through a 1-kc low-
pass filler. This signal is then delivered to the Reference Amplifier of the Base Band
Unit where the d-c error voltage is amplified approximately 2500 times and delivered
to a single-pole, R-C section, low-pass filter with a cutoff frequency of 2 cps. This
filter is physically located in the Gate Driver Amplifier. The d-c correction voltage
is switched by a relay in the Gate Driver Amplifier to a differential input of the DC
Amplifier in the record mode or to a differential input of the Gate Driver Amplifier in
the reproduce mode.
7. 2. 2.1 DC Amplifier
The purpose of the DC Amplifier is to amplify the incoming PAM signal approximately
10 times and establish a d-c reference level of approximately -2 {t 2) volts. These
functions are performed by using three dual -tr lode (6201) vacuum tubes and their
associated components . The first two cathode-coupled trlodes (VI and V2) act as s
comparison amplifier that amplifies the difference of the signals appearing on grids 2
and 7 of tube VI. The third cathode -coupled dual trlode (VS) acts as a parallel cathode
follower and furnishes a low output impedance to the Noise Filter. Zener diodes are
used to correct the d-c offset throughout the amplifier. A schematic diagram of the
DC Amplifier is shown in Fig. A-2.
Two inputs to the DC Amplifier are provided. One Input is the PAM pulse train from
the receiver; the second is the d-c reference level from the second low-pass filter in
the d-c reference feedback loop.
The PAM signal from the receiver is picked up at Jack J4 at & level of approximately
+6 volts dc. It is passed through Zener coupling diode CR7 where the level is reduced
to approximately zero volts dc. This signal is then applied to grid 2 of tube VIA. At
the same time, the signal input from the Reference Amplifier, via the second low-pass
filter, is applied to grid 7 of tube V1B through a network composed of resistors R9,
RIO, and Rll.
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in order to exercise adequate control over the d-c offset voltage, It Is necessary to
mJanoe we plate current being applied to VIA lu.d V1B, the first stage of the
amplifier. This is acoo^Usivst) by moans of potc .tio meter R2 (DC Balance no. 1).
While this adjustment ie bwiiv. mad? at Pi, the injui from the Reference Amplifier
is disconnected at jach Jf>. R^sv^tor 12 Is ;»djut. ed ao that the sync Interval (absence
of a data pulse) Is approximately -K C 2) volts* dc aa observed at test point TPS.
The output of V1B la passed \«. rough an offset voltage control network composed of
diodes CR1, CR2, and CHS that reduces the d-c voltage by 180 volts (1 10 percent).
The signal is then applied to grid 2 of V2A. The cathode of V2A is coupled to the
cathode of V2B, which is next to receive the signal. At the same time, there appears
on grid 7 cf V2B the signal from the output of V3, a part of the amplifier's internal
feedback circuit.
The output from the plate of V2B is passed through a second offset voltage control
network composed of diodes CR4, CR5, and CR6 which reduces the d-c voltage by
180 volts (± 10 percent). Capaoltors C2 and C3 are used to suppress the high-frequency
noise generated in the two Zener diode strings CR1, CR2, and CR3; and CR4, CR5,
and CR6.
The signal la then applied In parallel to grids 2 and 7 of V3A and V3B, the parallel
cathode follower. The output of thia parallel cathode follower Is delivered through
Jack JO to the Noise Filter. At the same time, this output is fed back to the grids of
V2B and V1B by means of the feedback resistors R9, RIO, R1S, and R16. Feedback
resistors R9 and RIO are used to control the overall gain of the DC Amplifier to
approximately 10.
There are three test points in the DC Amplifier. Test point TP1 provides a sampling
point for the Input from the receiver after passing through the 6-volt Zener diode CR7.
Test point TP2 provides a sampling point for the input from the Reference Amplifier.
Test point TPS provides a sampling point for the output of the amplifier. The input
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‘fifth
i-'
LMSD-288025
from the receiver, after passing through the 6-volt Zener diode CR7, is also delivered
to the Monitor Panel through jack J1 as the RCVR VIDEO DC position on Switch A and
Switch B.
A juniper between jacks J2 and J3 is normally used with the DC Amplifier. Should an
occasion arise when operation with the composite pulse train from some source other
than the receiver is desired, however, the jumper could be removed and the input
applied to jack J2, provided the d-c level is correct.
7. 2. 2. 2 Noise Filter
The purpose of the Noise Filter Is to improve the aignal-to-noise ratio of the composite
pulse train without introducing excessive crosstalk. It is composed of a time delay
circuit, a summing junction, a d-c offset adjustment circuit, and an output circuit.
Internal switching and separate plug-in output circuits permit use with both Vibration
and G-A Ground Sint ions. Input to the Noise Filter from the DC Amplifier Is at jack
J7 and its output to the Noise Filter Amplifier is at jack J8. A schematic diagram of
the Noise Filter, Including circuits used in both Vibration and G-A operation, is
shown In Fig. A-3.
With the SYSTEM switch on the Monitor Panel set at the VIB (Vibration) position, and
a Vibration plug-in unit in place, all Noise Filter components are in operation. The
output circuit is a single, series L-C section resonant at the composite pulse train
pulse repetition frequency of 40 kc. The delay of the time-delay circuit Is one-half of
the repetition frequency period, or 12. 5 microseconds. The filter is adjusted so that
the output reaches full amplitude during the time of one pulse and decays to zero during
the time the next pulse is sampled by the Datrac. The accuracy of this adjustment
determines the amount of crosstalk introduced by the Noise Filter, which can approach
zero.
The signal is delivered to grid 3 of a dual cathode follower composed of vacuum tube
VI and resistors R9 and RIO. The signal is also applied to grid 8 of VI after a
Revised 25 May 1960
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12. S-mlcrosecood delay produced by delay line L2. Variable resistor R5 of the di¬
vider composed of resistors R5 and R6 is used to control the amplitude of the delayed
Signal to oompsnsate for the attenuation of the undelayed signal Introduced by resis¬
tor* R2 and R3 and by the series- resonant output circuit. The signals present at
grids 3 and 8 are then summed by resistors R7 and R8 and applied to the series-reso¬
nant oirotiit oomposod of LI and the parallel combination of capacitors Cl and C3.
Capacitor C3 is a amail variable capacitor that is used tc tune the series-resonant
oiroult to the pulse repetition frequency. The output of the Noise Filter is the voltage
developed across capacitors Cl and C3.
D-C offset adjustment is accomplished by a circuit composed of tube V2 and associated
components. By varying the operating point of tube V2 with the DC Offset no. 1 con¬
trol, resistor R13, d-o current flowing out of the junction of resistors R7 and R8 can
be changed, and the resulting I-R drop becomes offset voltage. This adjustment is
made so that there is 3. 5 ( *0. 5) volts offset between jacks J7 and J8. Offset
conditions should always be checked when changing from one system (Vibration or
Q-A) to the other.
7, 2. 2. 3 Noise Filter Amplifier
The purpose of the Noise Filter Amplifier is to amplify the signal delivered by the
Noise Filter so that the peak-to-peak voltage with full modulation is 19 ( * 1 ) volts.
The signal level must be suoh that the sync level (absence of data pulse) is -9. 5
(±0. 26 ) volts. These functions are performed by using two dual-triode (6201)
vacuum tubes and one dual-triode (6463) vacuum tube, and their associated components.
The first two cathode-coupled triodes (VI and V2) act as a comparison amplifier that
amplifies the difference of the signals appearing on grids 2 and 7 of VI. The third
cathode-coupled triode (V3) sots as a parallel cathode follower and furnishes a low
output impedance. Zener diodes are used to correct the d-c offset throughout the
amplifier. A schematic diagram of the Noise Filter Amplifier Is shown in Fig. A-4.
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The signal Is delivered to the Noise Filter Amplifier at Jack J9 and applied to grid
2 of VI. At the same time, the signal appears at grid 7 of VI as feedback from cathode
follower V3. Plate current to VI is balanced by means of DC Balance no. 2. In order
to make this adjustment, it is necessary to dioconnect the input signal at Jack J9. Test
point TP8 should go to ground potential when the adjustment is properly made.
The output of plate 6 of tube VI is delivered to grid 2 of V2, the second cathode-coupled
dual triode, through an offset voltage control network composed of diodes CR1, CR2,
and CR3 which reduces the d-c voltage by 180 volts (-10 percent). Cathode 2 of V2
is coupled to cathode 8, which is next to receive the signal. At the same time, the
signal from the output of V3, a part of the amplifier feedback circuit, appears on grid
7 of V2.
The output from plate 6 of V2 is passed through a second ofiset voltage control network
composed of diodes CR4, CR5, and CR3 which reduces tba d-c voltage by 180 volts
( - 10 percent). Capacitors Cl and C2 are used to suppre? s the high-frequency noise
generated in the two Zener diode strings.
The signal Is then applied to grid 3 of cathode follower V3. The output of this half of
V3 appears Oil caunxie 2. This Output is delivered to gnu 7 of V2 and grid 7 of Vi
through resistors R7, R8, R9, and R13, which act as voltage dividers of a feedback
circuit within the Noise Filter Amplifier. This output is also coupled to jacks Jll and
J12. At the same time, a part of this output is delivered to grid 8 of V3 through reals'
tor R17 and variable resistor R18. The output of this half of V3 appears on cathode 7
and is ac-coupled to the Sync Separator in the Demultiplexer through jack J10,
Capacitor C4 acts as a blocking capacitor to prevent high voltage from entering the
Demultiplexer.
There are two adjusting points in this circuit in addition to DC Balance no. 2, which
was described earlier. Beth of these points, resistors R8 and R18, are adjusted with
the input from the Noise Filter connected to jack J9. Resistor R8 (Overall Gain) is
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set so that the peak-to-peak voltage with Ml modulation i» 19 (±1 ) volts at test point
TF3. H is advisable to recheck the adjustment of DC Balance no. 2 after resistor R8
is adjusted to assure that ground potential Is present without signal Input. Variable
resistor R18 (a-c gain) is adjusted so that the peak-to-peak voltage with full modula¬
tion la 15 2) volts at test point TP7.
The output at jack Jll is connected to the Reference Voltage Optional Clamp where a
switch either delivers the signal directly to the Datrac and Gate Driver Amplifier or
clamps it to a d-c reference voltage before delivery to the Datrac and Gate Driver
Amplifier.
There are three test points in the Noise Filter Amplifier. Test point TP6 furnishes
a sampling point for the input from the Noise Filter; test point TP7 furnishes a sam¬
pling point to the a-c video output to the Demultiplexer; and test point TPS furnishes
a sampling point to the d-c video output to the Roference Voltage Optional Clamp.
The Noise FiLter Amplifier has three outputs. One output is delivered to the d-c
coupled Anaiog-to-Dlgltal Converter. The signal 1b also fed ac-coupled to the sync
circuits in the Demultiplexer. Peak-to-peak amplitude of this output is 15 (*2) volts.
The third output, which is identical to the output going to the Datraq,is delivered to
the Gate Driver Amplifier.
7. 2. 2. 4 Reference Voltage Optional Clamp
A Reference Voltage Optional Clamp circuit is included in all Vibration and G-A Ground
Stations with record capabilities. The purpose of the clamp is to increase the relia¬
bility of the station in the record mode by allowing the operator an optional method of
restoring the correct d-c record level in case the main d-c correction circuit fails.
A schematic diagram of the clamp is shown in Fig. A-5.
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The clamp circuit is contained In a 2-3/4 in. by 2 in. box that is mounted an top of the
case containing the Reference Amplifier in the Base Band Unit. The • witch positions
on the clamp box are labeled CLAMP and SERVO. When the switch is in the SERVO
position, the clamp is eliminated from the circuit, and the reference level is furnished
by the d-c correction circuit. When the switch is in the CLAMP position, the d-c cor¬
rection circuit is eliminated and the clamp furnishes the appropriate d-c correction
level.
The clamp level is fixed at -9 <*0. S) volts by an SV-9 Zener diode. In order that the
d-c record levels remain approximately the same for the CLAMP or SERVO positions,
the main d-c correction circuit must be set up to match the clamp level.
7. 2. 2. 5 Gate Driver Amplifier
The Gate Driver Amplifier furnishes a gain factor of approximately 0. 33 and a d-c
voltage offset so that a zero signal at the vehicle multiplexer results in a zero signal
at the output of the Demultiplexer. This unit delivers the signal to the Demultiplexer.
This amplifier is made up of a comparison amplifier, a positive peak limiter, a cathode
follower, an offset control, and an output clipper. To facilitate switching between the
record and reproduce modes of operation, the Reference Amplifier low-pass filter is
included as a part of the Gate Driver Amplifier. A schematic diagram of this circuit
is shown in Fig. A-6.
In the record mode of operation, the Noise Filter Amplifier furnishes the input to the
Gate Driver Amplifier, hi the reproduce made of operation, the Datrac furnishes the
input to the Gate Driver Amplifer. The input Blgnal appears at jack J13 or J14, de¬
pending on the mode of operation, and is delivered to grid 2 of VI (a dual-triode
vacuum tube. €201, which acts as a cathode-coupled comparison amplifier) through
resistors Rl, R2, and R3 which serve as a voltage divider and attenuator. The output
of plate 6 of VI is passed through diode CR1 for offset voltage control, causing the
Revised 25 May 1900
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voitigi to drop 180 volt* ( * 10 poreont ). Capacitor C8 suppresses the high-frecruenoy
notes generated by diode CHI. Ths slgaal ia than passed through the positive peak
Uniter, composed of variable resistor R1S (limiter Mas), diode CR2, and oopooltor
C4, and is dsitvered in paraUel to grids S and 8 of cathode follower V2, a riuai-triode
(8809) vowmm tubs. The output of V2 (cathodes 2 and ?) is passed through a voltage
offset adjustment network composed of diodes CR3, CF4, and resistor H18 (DC Offset
no. 2). The signal is then deUvered to jack J17 through an output dipper composed of
diodes CB5 and CR7. This dipper prevents the output to jack J17 from going beyond
+10 or -8. 6 volts.
Also induded in the Gate Driver Amplifier is the second low-pass filter for the d-c
reference feedback loop* This filter consist* of resistor R4 and capacitors Cl and C2.
The input to the filter is from the Reference Amplifier. In the record mode of operation,
the filter output ia delivered to the differential input of the DC Amplifier. In the repro¬
duce mode of operation the DC Amplifier la not used and the filter output it, delivered
to the differential input (grid 7 of VI) of the Gate Driver Amplifier through resistors
Rll and R14. This unit filters out unwanted frequencies and prevents hunting.
7. 2. 2. 8 Reference Amplifier
The Reference Amplifier has a variable gain from 10 to 2500 to amplify the d-c cor¬
rection voltage. A gain of 2500 is normally used during operation of the Ground Station
in the Vibration mode. The outpu is delivered first to the second low-pass filter con¬
tained in the Gate Driver Amplifier and then to the differential input of the DC Amplifier
in the record mode at operation, or to the Gate Driver Amplifier in the reproduce mode
of operation.
The circuitry of this amplifier is described in detail in the Handbook of Operating and
Maintenance Instructions. A-12 DC Amplifier, supplied with the Ground Station. A
schematic diagram of the amplifier is shown in Fig, A-7.
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The input to the Reference Amplifier is of a differential type with respect to fround
in order to reduce ground loop problems. This Input from the 1-kc Filter card In the
Demultiplexer appears at Jack J28 at approximately 0 volte (within a few millivolt a)
when the feedback loop Is closed. If Instability of the video base line is noted, the
gain should be reduced until stability Is achieved. This instability will be noted at test
point TP11 In the Gate Driver Amplifier. Random noise may be present, but it is
filtered out by the second low-pass filter in the Gate Driver Amplifier. The output at
jack J23 should be C (*5) volts and must never exceed *10 volts as this level would
represent loss of operation of the d-c reference feedbaok loop. Although no demage
to equipment would result with the output approaching these limits of *10 volts, data
recovery accuracy of the Ground Station would suffer appreciably.
7. 2. 3 Demultiplexer, Record Mode
A functional diagram of the Vibration Demultiplexer in the record mode of operation is
shown In Fig. 7-8. The three principal functions of the Demultiplexer are: (1) to
separate the data sync pulse from the composite data signal for use as a dock pulse
lor the Demultiplexer and Analog-to-Digital Converter (Datrac) and to generate frame
sync pulses from the composite data signal; (2) to open and close the analog gates in
sequential fashion in order to separate the composite data signal into separate outputs;
and (3) to Bample the calibrate pulse that appears on Channel 1 alternately with the
sync pulse and send it through a low-pass filter as a d-c correction voltage to the
Base Band Unit.
Since the Ground Station is slaved to the vehicle dock, a dock signal must be recov¬
ered from the composite pulse train. This is done in the data sync generator where
a pulse is generated for every data pulse and sync interval in the PAM pulse train.
The phasing can be controlled to give the appropriate time relation between the clock
signal thus generated and the analog data pulses from the Base Band Unit.
One output of the data sync generator is used to drive the blr iy countdown that pro-
dvies the square-wave signals used for "ANDing" purposes In the matrices. The
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outputs of the matrices are the keying signals for the analog data gates which receive
their Input In the form of the PAM analog pulse trail from the Gate Driver Amplifier
in the Base Band Unit. These sequential keying signals to the analog data gates are
on separate lines and are connected to the appropriate analog data gates which open
and close In correspondence with the keying signals. The "on” time of any one high-
frequency data gate Is the clock period, or 25 microseconds. The "off* time is one
frame minus the clock period, or 175 microseconds. The "on" time for a subcom¬
mutated data gate is die same as the "on" for a high-frequency data gate, or 25 micro¬
seconds. The "off' time of the subcommutated data gate is eight frames minus one
clock period, or 1575 microseconds.
To keep the Demultiplexer in synchronization with the PAM pulse train (that is, to
open the appropriate analog data gate when each channel of the PAM pulse train is
delivered from the Base Band Unit), a frame synchronization pulse is used. Frame
synchronization pulses are generated in the frame sync generator which produces a
pulse whenever a pulse is missing in the PAM pulse train. To ensure that this pulse
is a valid sync pulBe and not a stray pulse as might be generated in the presence of
r-f noise interference or a faulty multiplexer, a certain amount of logic is incorporated
into the circuitry.
True frame sync occurs on Channel 1 alternately with a calibrate pulse. Therefore,
the train of potential sync pulses is delayed exactly eight channels by means of an
eight-bit shift register and compared in a logic gate with the potential frame sync
pulses being generated by the frame sync generator. This will produce a frame sync
pulse output only when the potential frame sync pulse appears on alternate frames.
Once apparent frame sync has been established, it is fed into a pate which opens to
receive a sync pulse only when one is expected as determined t> the high-frequency
binary countdown and matrix. When the sync pulse arrives, it oloses the gate and
blocks any spurious pulses. If the sync pulse does not arrive as expected, the sync
gate remains open until sync Is again established. This circuit performs the function
of blocking periodic and nonperiodic false sync pulses as well as the subcommutated
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Ryuc polMi whioh vpMn M a nonperiodic syno pula* to the high-frequency binary
>i addition, a Mboommutated synchronisation pulse is needed to oontrol the subcom-
mutated binary oowtdovn and matrix. This pulae ia derived by sampling the output
at the frame sync generator only during Channel-8 time by way of a keyed gate that is
controlled by the high-frequency binary countdown and matrix. The output of the keyed
gate la delivered to a aub commutated sync gate which opera t a in the same fashion as
the high-frequency gate except that it ia controlled by the subcommutated countdown
and matrix.
The two signals appearing at the output of the high-frequency and subcommutated sync
gates are delivered to the Digital Record Electronics for recording on a single digital
trade. These signals are combined onto one line by means of an OR gate.
7. 2. 3. 1 Data Sync Separator
The purpose of the Data Sync Separator ia to extract the data sync or clock information
from the composite pulse train (a-c video). The Data Sync Separator is composed of
the following circuits: damp and clipper, band-pass filter, pulse shaper ; clipper
amplifiers, one-shot, emitter follower, and blocking oscillator. A schematic diagram
of the Data Sync Separator is shown in Fig. A- 8.
Clock output occurs in the form of a square wave or pulse; data sync is in the form of
s pulse only, dock information is in time pn&se with data Bync information. Data
aync output ia actually clock information which haa been delayed so that keying pulses
for die data gates occur at a time when interchannel crosstalk is at a minimum, rhe
Q of the band-pass filter Is such that clock and data sync outputs are present when as
many as approximately 30 consecutive data pulses are missing. Operation of the
Data Sync Separator ceases whenever more than approximately 30 consecutive data
pulses are missing.
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LOCKHEED AIRCRAFT CORPORATION
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L.MSD- 288025
The composite pulse train Input (a-c video) from the Noise Filter Amplifier appears
at pin J. It then enters the damp and clipper circuit, which Is oomposed of diodes
CR3 and CR4, transistors Q3 and Q6, and associated components. This circuit re¬
stores the d-c level to the a-c video and clips below minimum data level. Resistor
R13 Is adjusted so that positive peak clipping oocurs at 1. 5 (*0. 2) volts. Test
point TP1 - the Junction of diode CR4 and resistor R13 - should be observed when this
adjustment is being made.
The output from the clamp and clipper circuit passes through the emitter follower
composed of transistor Q€ and resistor R19, Into the band-pass filter. This band¬
pass filter Is a ringing, oscillator-type circuit In which the resonant frequency is that
of the sampling rate of the composite pulse train. The output level control of the clamp-
and-clipper circuit, resistor R19, Is adjusted so that the peak-to-peak amplitude of the
output sine wave at the Junction of capacitor C14 and diode CR7 Is 15 ( * 1 ) volts. Fine
tuning of the tank circuit is made by adjusting capacitor C13A.
The signal Is coupled Into the pulse shaping network through capacitor C14. Transis¬
tors Q14 and Q17, diode CR7, and associated components act as a dual emitter follower
and clamp circuit. Its output is fed into the clipper circuit composed of diodes CR9 and
CR10, transistor Q19, associated components. SLlicoo diodes OR9 and CR10 chancre
the sine wave from the dual emitter follower into an approximately square wave.
This square wave Is coupled into the clipper amplifiers through the emitter follower
composed of transistor Q19 and resistor R52. There are two saturating-type amplifier
stages and two emitter follower stages In the clipper amplifier circuitry. The two
amplifiers are transistors Q2 and Q7 with their associated components; the two emitter
follower stages are transistors Q5 and Q9 with their associated components. The signal
is amplified but not inverted, and the output is fed into four succeeding emitter followers
in parallel. Output of the clipper amplifiers, which is now a square wave, passes through
the emitter follower composed of transistor Q8 and associated components to pin 3 1 and
through the emitter follower transistor composed of transistor Q10 and associated
Revised 25 May 1960
7-27
LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
LM8D- 288025
■PBH WMrtt to pte R . These two clipper amplifier outputs are then delivered as clock
ftyttl* ««VM to tfa# Right- Bit Shift Register at pin M and to the Frame Sync Separator
#9tl A. Output of the dipper amplifiers is also fed to the one-shot through the
— fttwr follower oompoeed of transistor Q12 and assodated components. Positive-
going portions of the square wave trigger the one-shot, which is composed of transistors
Q1S snd Qlg and thslr aasociatsd component a. The variable delay of 4 to 25 micro¬
second# is adjusted fay resistor R39 In such a manner that the data gates are keyed when
minimum Interchannel eroaataik occurs. The one-shot output (monitored at the junction
of oapsottor Ctl and resistor R51) is s series of positive pulses. These pulses fire a
blocking oscillator composed of transistors Q18 and Q16, transformer Tl, and associated
components. The output of the blocking oscillator consists of data sync pulses which are
fed to the Pulse Sequencer and Frequency Divider at pin b. Finally, the output from the
clipper amplifiers passes through an emitter follower oompoeed of transistor Q1 and Its
assodated components; e differentiating circuit composed of capacitor C4t diode CK2, and
resistor R8; and an emitter follower composed of translator Q4 and associated com¬
ponents to pin T for delivery as a series of positive clock pulses to the Data Sync
Delay Record.
7, 2. 3. 2 Frame Sync Separator
The Frame Syno Separator produces a pulse whenever a data pulse Is absent in the
composite pulse train. This unit is adjusted so that whenever the level of a data pulse
falls below s 0. 5-volt level with reference to the base line, a pulse is produced. The
unit Is made up of the following functioning circuits: d-c restorer, positive peak
dipper, adder, decision level inverting amplifier, one-shot, and three blocking oscil¬
lators. A schematic diagram appears in Fig. A-9.
The composite pulse train (a-c video) input is delivered to pin J . It is then clamped
to a few tenths of a volt, positive d-c, by means of the d-o restorer composed of
capacitors C2 and C4, diode CR2, diode CR11, and resistor R3.
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LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISIC >1
The signal is then delivered to the poaillve peak dipper set to clip below minimum
ita level, which is approximately +2 volts as monitored at test point TPl. This
dipper la composed of transistor Ql, diode CR3, and associated components. The
dipping level is adjusted by varying resistor R8.
The cloak square wave from the Data Sync Separator appears at pin R. It is delivered
to the clock blocking oscillator composed of transistors Q6 and Q7, transformer Tl,
and associated components. The output of thlo blocking oscillator is delivered to
pin S as reset pulses to the Eight -Bit Shift Register. It also Is delivered to the one-
si ot composed of transistors Q8 and Q9 and associated components. This multivibrator
introduces a variable time delay from 4 to 2S mioroseoonds. The time delay is set by
adjusting resistor R26. The output is delivered as dock pulses to a delayed blocking
oscillator composed oi transistors Q10 and QI1, transformer T3, and associated com¬
ponents.
The output of this blocking oscillator is delivered to the adder composed of resistor
RIO. This adder oomblnes the dipped composite pulse train and delayed data sync.
Resistor R26 in the one- shot circuit is adjusted so that the negative-going blocking
oscillator pulses are centered on the data pulses as they are monitored at test point
TP2.
The output of the adder is delivered to the decision level Inverting amplifier composed
of transistors Q2 and Q3, diode CRS, and associated components. This amplifier
selects the blocking oscillator pulses which coincide with the absence of data pulses
and provides a positive-going pulse to fire the output blocking oscillator oomposed of
transistors Q4 and QS, transformer T2, and associated components.
The output blocking osoillator provides sync pulses which are delivered to the Eight-
Bit Shift Register and the Sync Selector at pin P, Resistor Rio is adjust* so that
the blocking oscillator fires reliably whenever a data pulse is absent but will not fire
under any other conditions. A good setting of RIO would be halfway between {!) the
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LOCKHEED AIRCRAFT CORPORATION
MISSILES ond SPACE DIVISION
LMSD- 288026
setting that jiut begins to fir* the output hlocklng oscillator at dock rate, and (2)
the setting that just atop* firing the output blocking oscillator at data pulse absence
rat*. Tfeta setting oan be monitored at pins J and P.
7.1 $.8 Right-Bit Shift Rsglstsr
Th* purpoaa of the Eight-Bit Shift Register la to store data pulse absence or sync pulse
Information for eight clock periods (of time) and present to a succeeding AND gate direct
sync pulse outputs and stored sync pulse outputs.
This unit Is composed of a series string of nine delay-coupled flip-flops, four output
emitter followers, and a clock driver. The schematic diagram is shown in Fig. A- 10.
The first flip-flop acts as a buffer stage for the succeeding eight units in the shift
register. It stores the sync pulses until the dock shiftB this Information Into the first
storage flip-flop.
Three Inputs are provided: Reset (clock) pulses from the Frame Sync Separator appear
at pin S; sync pulses from the Frame Sync Separator appear at pin ?; And the clock
square wave from the Data Sync Separator appears at pin ML
The reset pulse on pin S pinse* through diode CRl and saturates transistor Qi. v lien
a sync pulse Is present at pin P, current passes through diode CR2 causing transis >r
Q2 to saturate and the collector of transistor Ql to go tc high potential. This allow,
capacitor C5 to charge through RIO because diode CR7 is back-biased when translate r
Q2 of the dock driver is cut off with a negative clock pulse. When transistor Q2 is
saturated with a positive dock puise, diodes CR7 and CR£ conduct because of the pre¬
vious charge on capacitor C5. This current flowing through diode CR8 cuts off transis¬
tor Q4 and saturates transistor QS, thus setting up the first storage flip-flop.
\
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LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
LMSD- 288025
In a like manner, tbo absence of a sym pulse will cause the first storage stage to be
set up in the opposite way with transistor Q5 cut off and transistor Q4 saturated. This
process continues through succeeding stages until the last stage is reached.
Two outputs are provided by the output emitter followers. The stored sync pulses are
delivered to pin U for transfer to the Programmer, while the direct sync pulses are
delivered to pin K for transfer to the Programmer.
7. 2, 3. 4 Programmer
The purpose of the Programmer is to <1) provide a keying pulse to the sync gate every
other frame at the Channel 1 position and (2) provide the ANIdng logic associated with
the Eight-Bit Shift Register. The Programmer is composed of an AND gate and a
flip-flop. A schematic diagram is shown in Fig. A-ll.
Inputs to the AND gate (pins K and U) are provided by the Eight-Bit Shift Register.
Input at pin K corresponds to the absence of a data pulse, and input at pin U corre¬
sponds to the presence of a data pulse delayed for eight bits of time. Diodes CR1
and CR2 and the emitter follower composed of transistor 01 and resistor R1 provide
a pulse upon the time-coincidence of input i at K and U.
The flip-flop, which is composed of transistors Q2 and Q3 and associated components,
is triggered by the Channel 1 keying pulse from the data gate. This pulse appears at
pin d . The flip-flop output, which is coupled through the emitter follower composed
of transistor Q4 and resistor R12, constitutes a keying pulse to the sync gate end is
delivered to pin a .
7. 2. 3. 5 Sync Selector
The purpose of the Sync Selector is to combine sync pulses for rocording purposes in
such a manner that only sync gate and keyed gate circuitry need be used to produce
Revised 25 May i960
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LOCKHEED AIRCRAFT CORPORATION
MISSILES and 'PACE DIVISION
LM8D- 288025
both main und subconunutated frame sync while In the reproduce mode, A schematic
diagram of the Sync Selector is shewn in Fig. A- 12.
There are two inputs to the Sync Selector. Sync pulses from the Eight-Bit Shift Register
AND gate appear or pin Z. Sync pulses from the Frame Sync Separator appear on pin
P ,
S/no pulses entering at pin P paas through an emitter follower composed of transistor
Ql and resistors R2 ai d R4. These pulses then enter the gate circuit, composed of
vransistors Q3, Q4, aocl 05 and asaoclated components, at the emitter of transistor Q4.
Series switch Q4 shunt switch Q5 are keyed by a pulse amplifier composed of transis¬
tor Q3 and resistors R3 and &7. This pulse amplifier is operated by aubcommutaled
keying pu»*es, wide!' appear on pin K in such a manner that the presence of a keying
pulse opens the gate and the abs&nce of a keying pulse closes the gate. Output pulses
hom the gate are passed through the emitter follower composed of transistor Q7 and
resistor Rl£ for delivery to yin d as the subcommutated sync pulse to the sync gate.
Output pulses from the gate arc alec- passed through the emitter follower composed of
translator Q6 and resistor Rll and are coupled through capacitor C4 for delivery to
the blocking oscillator the* is composed of transistors Q8 and Q9, transformer Tl, and
associated components.
3yr<c pul also enter at pin Z and pass through an emitter follower composed of
transit, or Q2 end resistor R6 and are then coupled through capacitor C3 for delivery
to the blocking oscillator.
The blocking oscillator is fired by current pulses from either capacitor C3 or capacitor
C4. Tne positive output pulses of the blocking oscillator are delivered to pin f as
composite frame sync for the Digital Record Electronics.
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MISSILES and SPACS DIVISION
LMSD-288028
7. 2. S. 6 Sync Gate
The purpose of the Sync Gktte la to permit frame eync poise* to ha generated only
Booh pulses are anticipated. Syne pulses which are not true sync pulses are seas
produced by preceding rync separation circuits because of r-f iaterferwoe. The
If a pulse can be supplied to arrive at a time when frame sync is eapected sad thh
pulse keys a gate that follows tbs frame syne logic circuitry, the ofcsaoe ei pswdi
false frame sync is gr eatly reduced. The Sync Gate is mads up of two owe rhstr.
blocking oscillators, a flip-flop, a dual emitter follower, and a gate. Urn ssfeem
diagram for the Sync Gate ts shewn In Fig. A- 12.
There are two Inputs to the Sync Gate. Keying pulses are delivered to pis a . JQ
pulses are delivered to pin Z . Frame syne output Is os pte f .
The keying pulse from pin a resets the flip-flop so— gsasit «f If— stators <p and f
and Associated components so that the output ow the enuHter Mlemr eeopuaed of
transistor Q1 and resistor R2 (TP2) turns on the gats coiupnaid of timdstw QM
resistors R36 and R37.
The anticipated sync pulse appears on pin Z. K Is s poattivs pdas and ts ttfMtktU
by capacitor Cl, diode CR1, and resistor R1 so that the positive- pdag portico of tfei
pulse triggers the one shot compowu o£ iraunowi $2 ana Qt sad rxracl start ssm~
ponents. This one-shot fires blocking oscillator thk 1, composed of translator* 9*
and Q7, transformer Tl, and associated eomponduUi, at a time several mlornwe nulls
after the initial generation of the aync pulse in the Frame Sync gspsralor. The reeaee
for this delay la that aync pul sea generated In the Frame Sync Separator are appreod-
mately in time phase with the data sync and that resetting of the pulse sequencers by
the output of the Sync Gate (pin f) must occur slightly after triggering by the data syno.
This delay can be varied between 4 and 25 microseconds by adjusting resistor US, but
the delay Is usually of the order of 3 ( * 1 ) microseconds.
LOCKHEED AIRCRAFT CORPORATION
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LMSD-888026
A* PMittri going net put pul ess of Moolrtng oscillator no. 1 are delivered to tha dual
easftiear ftritawnr tMpoari of tmiWori Q9 and Qll and iNoeWad components. Hh
*dpl ltd af i» *wl wttttr Mtowr ti mu d Ud point TP1, and la adjusted by
dBMhhCf ihHlMft jraatotaa m to IQ (^2.8) volte pcah-io-paafc.
•» pl»«MVMai af tnaddtr Q1S and raalatora BSfl and R87, which waa opened by
fltoa—tonaf tha ihp thg yami a poatdn pulse that fires Nooklng oscillator no. 2
sssapMKd af tramdators 4gU ad Q14, transformer T2, and aaaociatad components.
S to delivered to pin f aa
QtandQtOand aaaociatad
to Inara that tha
ha adftatad
after the
franc ayao and to one-
oomponeuta. Oca-shot
will peas anticipated
ao that tha flip-flop
of a frame sync
to a pin add ah to hayed "on" by t) arrival of a pulao which
id pa pin. It la hayed "off If the anticipated aync pulse
t*. M no aatlolpatad ayao pulse arrives, the Sync Gate re¬
nt syne pulse arrives.
«i >a^ ^ ttMSUMM
The Zero Data fidectar eeleote the pedeatal levels from the oonpoette pulse train which
eentetas alternating pedeatal levels and eyne levels on Channel 1. The pedeatal levels
are fed to the first low-peas filter la the DC reference feedback loop. A schematic
diagram of the Zero Date Selector la shown In Fig. A- 14.
Channel 1 keying pulses from the Data Gate enter on pin d into an emitter follower
composed of transistor Q1 and resistor B4. It la ooupled through capacitor C4 to the
trigger input of the flip-flop oompoeed of diodes CR1, CR2, and CR3j transistors Q2
and Q3t and associated components.
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LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
LMBD-288025
The main frame ayno from the Sync Gate enters on pin f and resets the flip-flop sc
that the output at the emitter follower composed of transistor Q4 and resistor R21 Is
positive only when pedestal pulses appear in the pulse train. The output of this emitter
follower Is "ANDed” with the output of the emitter follower composed of transistor Q1
and resistor R4 by means of an AND gate composed of diode CR4 and resistor HI 7. The
output of this AND gate turns transistor Q7 an only during alternate frames. The out¬
put at the collector of transistor Q7 keys the keyed gate composed of transistors Q6
and Q6 and associated components. The keyed gate permits only alternate Channel 1
data (pedestal pulses) to be applied to the d-c reference feedback loop. The output of
this keyed gate is delivered to pin V .
7. 2. 3. 8 Frequency Divider
The purpose of the Frequency Divider is to divide the repetition rate, or frequency,
of pulses by factors of two, four, or eight. Reset and set Inputs are available for each
of the three cascaded flip-flops, or binary counters, so that outputs can be phased in
any desired manner. A schematic diagram of the Frequency Divider Is shown in
Fig. A-15.
When It is desired to operate pulse sequencers at rates below that of clock, a frequency
divider is Inserted between the source of clock pulses and s low- speed pulse sequencer.
As the low-speed sequencers must sequence at certain times, reset pulses must be
properly applied to the flip-flops In use. In the Vibration operation, the frequency is
divided by eight.
All three flip-flop stages and associated output emitter followers In the Frequency
Divider are similar. As shown In the schematic diagram, data sync pulses are de¬
livered as trigger pulses for the Frequency Divider at pin b . Set and reset pulses
are furnished for each of the three flip-flops. Output in the form of trigger pulses
for the subcommutated pulse sequencer are delivered to pin P.
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LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
LM8D- 288025
7. 2. 3. • light Channel Pulse Sequencer
Tha purpose of tha Eight Channel Pula* Sequencer la to provide eight channels of pulses
In time eequenoe. Seven flip- flops and eight AND gates are arranged to accomplish
thia purpose. A schematic diagram of the Eight Channel Pulse Sequencer la shown In
Fig. A-18.
The output pulses of the pulse sequencer are used to key data gates. The trigger pulses
determine the irate at which the output pulses advance. The reset pulses determine the
phase of the output pulses In relation to the no. 1 output pulse.
The AND gates are driven by flip-flop outputs, which are Isolated by individual emitter-
follower stages.
7. 2. 3. 10 Data Gates
The purpose of the Data Gates la to provide eight data gates which are keyed by the out¬
puts of a series of AND gates. These AND gates are In turn keyed by pulses from pulse
sequencers. The Data Gates unit is made up of 12 emitter followers, eight AND gates,
and eight data gates. A schematic diagram of this unit Is shown in Fig. A- 17.
For any one of the AND gates to produce an output pulse, two coincident input pulses
must be present. For example, to produce an output from AND gate 3, input pulses
must be i resent at pins ] and V; for an AND gate 2 output, Input pulses must be
present at pins ] and X .
All AND gates are composed of a single diode and a single resistor and possess two
inputs and one output. The signal level appearing on Pin J Is applied to one input of
AND gates 1 through 4 through an emitter follower composed of transistor Q2 and
resistor R3. The signal level appearing on pin M is applied to one input of AND gates
S through 8 through an emitter follower composed of translator Q7 and resistor R9.
. ’.evlsed 25 May 1960
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LOCKHEED AIRCRAFT CORPORATION
MISSILES ai d SPACE DIVIS ON
L USD- 2880 25
The other input to AND gates 1 through 8 is supplied from app opri&te pins and
emitter followers. Outputs of AND gates 1 and 8 are ooupled through emitter follow¬
ers to pins d and K , respectively, as keying pulse outputs. These outputs key
individual data gates 1 through 8.
All data gates are identical. Each data gate is composed of an inverting pulse ampli¬
fier. a shunt translator switch, and a series transistor switch. Data gate 1 will serve
as an example of circuit operation.
AND gate 1 output pulse rises and falls between -IS and -5 volts. When the voltage
Is greater than approximately -10 volts, transistor Q21 is turned on. The collector
of this translator, which serves as an lnvsrtlng pulse amplifier, drops to approximate¬
ly -10 volts. This voltage turns off transistor Q29 and turns an transistor Q13. Tran¬
sistor Q29 is the shunt switch and Q13 la the series switch. When the output from the
AND gate drops below approximately -10 volts, transistor Q13 turns off and turns on
Q29.
Whenever an output from an AND gate appears, the data gate will open and d-c video
from the Gate Driver Amplifier will appear. Whenever there is no AND gate output,
the data gat.« output will present a short circuit with respect to ground.
The gated Outputs from data gates 1 through 8 are delivered to appropriate pins for
delivery to display electronics.
7. 2, 3, 11 Data Sync Delay Record
The Data Sync Delay Record circuit delays the clock pulses so that sampling In the
Datrac occurs at a time when crosstalk Is at n minuroum. At this time, the Data
Sync Delay Record delivers a command pulse to the Datrac. A schematic diagram
of this unit is shown In Fig. A-18.
Revised 25 May 1960
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LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
LMSD-288025
Tilts otrouit is oonpcsed of s one-shot which provides variable delay, s blocking
oeclllatar, sad an smittsr follower.
Tbs input of positive clock pulses from the Date Sync Separator is at pin a . The
pulses are delivered through an emitter follower, compose! of transistor Q1 and re¬
sistor R-\ to die one-shot, composed of transistors Q2 ai.d Q3 and associated compo¬
nent, where a suitable delay is added to the clock Information. Delays from 4 to 25
microseconds are obtained by adjusting resistor R5. The output of the one-shot is
coupled through capacitor C8 to the blocking oscillator composed of transistors Q4 and
Q5, transformer Tl, and associated components.
Positive command pulses to the Digital- to- Analog Converter leave the blocking oscil¬
lator at pin N .
7. 2. 4 Output Filters and Amplifiers
The purpose of the Output Filters and Amplifiers (Fig. 7-9) is to take the demultiplexed
series of pulses and smooth them out in such a fashion that the output can be reproduced
continuously and proportional to the signals applied to the vehicle multiplexer.
Three Filter Boards (2 kc, 1 kc, and 250 cps) srs p? evince* to interpolate the data
pulses from the main and subcommutated data gates . A schematic diagram of a Filter
Board is shown in Fig. A-19. The filters have a cutoff frequency of approximately
0. 4 times the pulse repetition rate per channel. This results in a 2-kc cutoff frequency
for the high-frequency channels and a 250-cps cutoff frequency for the eubcommutated
channels. The filters pass all frequencies in the range of 0-2000 epe corresponding to
the modulation frequencies and attenuate all higher frequencies, including the sampling
frequency, at least 40 db. The filters used with the subcommutated channels pass all
frequencies in the range of 0-250 cps corresponding to the modulation frequencies and
attenuate all higher frequencies, including the sampling frequency, at least 40 db. The
filters are connected by way of a patch panel to the output amplifiers which are capable
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LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE OIVI5ION
Fig. 7-9 Vibration Output Filters and Amplifiers
LM SB-288025
of delivering 100 mm *o &e galvanometers of the Visual Display Ufrit (Visicorder) or to
an external load.
Characteristic impedance of both types of Filters is 10K, and two outputs per filter are
provided, one being one-eighth the amplitude of the other, so that display circuit gains
do not require adjustment when the duty factors are changed, as in the case of switch¬
ing from main to subcommutated channels.
In addition to the 250-cpe and 2-kc filters that are used only for interpolation, 1-kc
filters are used In the d-c reference servo loop. Here, - a 1-kc cutoff frequency ade¬
quately filters the 2. 5-kc fundamental frequency component of the sampled input with¬
out causing Instability in the servo loop. The Output Filters and Amplifiers perform
the same function and operate in the same manner in both the record and reproduce
modes of station operation.
7. 2. 5 Visual Display Unit
The Visual Display Unit (Vlslcorder) reproduces the outputs of the Oitput Filters and
Amplifiers in oscillograph form and thus furnishes a simultaneous time history of the
seven Information channels of the Demultiplexer output. Adjustments on the Patch
Panel allow the operator to select any or all of the channels of information for display
on the Visicorder.
The theory of operation and maintenance procedures for the Visicorder are described
in detail In a publication of the Heiland Division of Minneapolis-Honeywell titled
Operation Manual — Honeywell Model 906B Visicorder Oscillograph. Publ. No. 850320,
Denver, Colorado, Sep 195£,
7. 2. 6 Analog- to -Digital Converter
The Anaiog-to- Digital Converter (Datrac) converts every pulse of the PAM composite
pulse train into a nine-bit digital word.
j vised 25 Ma\ 1960
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LOCKHEED AIRCRAFT CORPORATION
MISSILES ond SPACE DIVISION
LMSD-288025
Included in the Analog- to- Digital Converter la a sample and hold circuit that samples
the peak value of every pulse and holds it for digitisation. This circuit, which is con¬
trolled by the data sync pulse from the Demultiplexer, is turned on for approximately
2 microseconds by the data sync pulse and holds for approximately 23 microseconds.
After a short stabilising interval, the converter operates at a rate of 2 microseconds
per bit and converts the sample and hold signal into a nine-bit digital word in 18 micro¬
seconds. These nine bits are temporarily stored and applied to the Digital Record
Electronics.
The theory of operation and maintenance procedures for the Datrac are described in
detail in the instruction manual Datrac Analog- to- Digital Converter published by
Epsco, Inc. , Boston, Mass. Mddlficatlons made in the Datrac are dee ibed in this
manual. Schematic diagrams of the modifications are shown in Figs, a- 20, A- 21,
A-22, A-23, and A-24.
In performing the function of recording and reproducing information for the PAM-FM
Ground Station, it is necessary to convert analog information into digital form for re¬
cording and to convert digital information into analog form for reproduction. The
conversion process is accomplished by a device supplied by Epsco, Incorporated, under
the trade name of D&crae. The model supplied for use in the Ground Station la the
B-609SM2, modified for the special requirements of the Ground Station. The Datrac
B-609SM2 (a modified version of Model B-611) is documented in an inatructlon manual
for the Datrac Analog- to- Digital Converter, Models B-611 and B-613. The purpose
here le to document those modifications made to the B-611 and the B-6098M2 for use
in the PAM-FM Ground Station.
The modifications Include:
e Addition of special high-speed sample and huld circuitry
• Addition of relays for converting between digital- to-an&log and analog-to-
digital modes
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• Gain of analog output circuitry ao tbat Input and output lavel (*10) volte) la
the name
• Reduction of notaa interference during digital- to- analog operation
e Removal of flrat and aeoond bita of die 11- bit total
e Addition of monitor point* to all output* to Record Amp lift ere
e Addition of operate output connectors for the following signals:
(1) Datrac command
(2) Conversion complete
(9) Serial pulse train
(4) Analog output
A brief description of die two modes of operation of the modified Datrac will be included
here.
In the analog- to-digltal mode of operation, the first event to occur is the arrival of a
Datrac command pulse. This pulse does three things; (1) it starts the sampling
prooess by operating the sample and hold switch-driver circuitry, (2) it starts the
digitisation process which actually begins with the third of 11 bits approximately 6
microseconds later, and (3) it clears all digital data from the previous conversion.
Si
on e and two have been removed from the 11-bit converter in order to give nine-
bit Informs: don and to allow stabilization of the Bample and hold circuitry and the am¬
plifier following the sample and hold. The sampling interval begins with the arrival
of the Datrac command pulse and lasts approximately 1. 5 microseconds. The memory
of the sample and bold circuitry then holds data voltage for approximately 23. 0 micro¬
seconds, at which time digitization is complete and a conversion complete pulse (used
to clock data onto the magnetic tape) is produced. Digitization of nine bits, beginning
with the third and ending with the eleventh, is performed at the rate of one bit for even
2 microseconds.
In the digital- to- analog mode of operation, conversion <s completed in only 6 micro¬
seconds. In thia process, the first event to occur is the arrival of r clear pulse from
7-42
LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
LMSD-288025
the Delay Command Pulse circuit contained in the Record u<d Raproduoe Electronics.
The next event to occur is the application, in parallel, of nine bits of digital data from
the Data Storage and Qate circuits. As the last event, approximately 4 microseconds
later, analog data appears for delivery to the Demultiplexer.
Figure 7-10 illustrates the analog-to-digltal conversion sequence. The externally ap¬
plied command pulse Initiates digitisation and sampling and the timing of the digitisa¬
tion of nine individual bits of Information. Completion of the conversion la marked by
; conversion-complete pulse after a total elapsed time of approximately 24. 5 micro¬
seconds.
The individual conversions necessary to make the Dstrac B-611 compatible with the
PAM-FM Ground Station are discussed in the following paragraphs.
In order to record the value of data pulses with a minimum of crosstalk and allow
digitization time, this data must be sampled In as short a time aa possible. The spe¬
cial high-speed sample and hold circnitry samples in only 1. 5 microseconds and holds
the data value for as long a time aa is necessary to perform digitisation, i. e. , 24. 5
microseconds. The sample and hold equipment is contained on ta» plug-in chassis.
Chassis no. i contains an input amplifier composed of an operational amplifier end
associated network. Chassis no. 2 contains a blocking oscillator, a switch driver,
a switch, a holding capacitor, a bias current source, and an operational amplifle and
associated netwjrk.
Analog voltage from the Base Band Unit appears on terminal 32 of Chassis no. 1
(Fig. A- 20) for delivery to the operational amplifier and network oomposetl of resis¬
tors Rl, R2, R3, R4, R6, and R7. The operational amplifier is composed of one-half
of vacuum tube V3, vacuum tubes VI and V2, and associated components. The gain of
this combination of operational amplifier and network is -1 as the ratio of R^/R^ is
unity. Its output is delivt ?ed to the cathode follower composed of one-half of vacuum
tube V3 and associated components. The output of this cathode follower Is delivered
7-43
LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
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LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
Fig. 7-10 Analog- to-Digita Conversion ]?rooess
to terminal 24 and then to terminal 14 on Chassis no. 2 as input to a diode switch
composed of vacuum tubes V4 and V5. The overall gain from tern: .nai 32 to terminal
24 on Chassis no. 1 is approximately 0. 85* The out put nt i or rhinal zA t* h#*twn*?n nn-
proximately +lfj and -5 volts.
Datrac command pulses from Chassis no. 8 appear on terminal 12 of Chassis no. 2
for delivery to a blocking oscillator composed of vacuum tube Y6, transformer Tl,
and associated components. These Datrac command pulses of +20 volts amplitude
override the -15-voit bias on grid 2 of V8 and force current to flow from cathode 3 of
V6 through capacitor C6 to produce positive voltage on grid 7 of V8. Current, now
flowing through transformer Tl to plate 9 of V6, Induces voltage across resistor R66,
further increasing the positive voltage on grid 7 of V6. The right half of vacuum tube
vo eonaucts until me cnarRu on capacitor t,o uropts cnougu to return the tube to me
cutoff state.
The resulting blocking oscillator pulse Is delivered to transformer T2 of the switch-
driver circuitry which is composed of transformer T2, and vacuum tubus V7, VS, and
V9. Transformer T2 provides positive and negative pulses. The positive pulse is
delivered to a cathode follower composed of vacuum tube V8 and resistor R32, and the
negative pulse is delivered to a cathode follower composed of vacuum tube V7 and
resistor R33. The network composed of resistors R34 and R35 and capacitor C7 pro¬
vides approximately +37 volts of bias to vacuum tube V7. The network composed of
resistors R38 and R37 and capacitor C8 provides approximately -30 volts of bias to
— - — — a..v« *ra
vacuum tuw v v.
If no pulses are being delivered to the switch-driver circuitry, sufficient current flows
through resistor R20, diode vacuum tube V9, and cathode follower V8 to produce ap¬
proximately -20 volts on the plates of vacuum tubes V4 and Vb of the diode switch.
Likewise, sufficient current flows from cathode follower V7 and diode V9 and through
resistor R39 to produce approximately +40 volts on the cathodes of V4 and V5 of the
diode switch, Under these conditions, diodes V4 and V5 are nonconducting and holding
capacitor C9 is effectively tied to the open grid 7 of vacuum tube V10.
7-45
MISSILES and SPACE DIVISION
LOCKHEED AIRCRAFT CORPORATION
i.MsrK2HHn:!n
When jmlmo art- delivered to the switch-driver from the blocking oscillator, bias
voltages for V7 and V8 are overridden no that the currents In both halves of diode V9
are Interrupted for the duration of the sampling interval, i.e. , for approximately 1. B
microseconds. This means that current flows from +300 volts at terminal 2 through
resistor R38, both halves of diodes V4 and V5, and through resistor R39 to 200 volts
on terminal 3, With the diode bridge conducting, data from Chassis no. 1 permits
supply current to charge holding capacitor C9 to data level.
The voltage level which appcn rs on holding capacitor C9 is delivered to the open grid
7 of vacuum tube V10 of the Operational amplifier composed of vacuum tubes VlU. Vll,
and V12, and associated components. Gain of this combination of operational amplifier
and the network composed of resistors R61, R82, and R63 Is adjusted by varying R63.
Overall gain Is adjusted to approximately 3 . The sampled output is delivered to
terminal 25 of Chassis no, 2 a« the input voltage to the Datrae summing junction.
7.2.7 Digital Record Electronics
Digital Record Electronics are used to record the digital word generated by the Datrae,
the composite frame sync, and the clock signal In paralled In Non- Return-to- Zero
(NRZ) form on the magnetic tape on command of the conversion complete pulse from
the Datrae, Digital Record Amplifier, Frame Sync Storage Record, and Pulse Ampli¬
fier cards make up the record electronics. A functional diagram of the Digital Record
Electronics is shown In Fig. 7-11.
The conversion complete pulse occurs approximately 0.5 microsecond after the
digitization Is complete. This pulse is amplified and delivered as a clock signal to
all digital record amplifiers and is recorded on one of the digital tracks as the clock
signal. It la also used to reset the Frame Sync Storage Record circuit.
Composite frame sync is applied to the frame sync storage circuit which, In turn, ap¬
plies a "one” to the Digital Record Amplifier. The occurrence of a conversion com¬
plete pulse will clock this Information onto the tape from the Digital Record Amplifier
7-46
LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
t
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COMPLETE
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ANALOG -TQ-
OIGITAL
CONVERTER
COMPOSITE
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BINARY
BITS
FROM
ANALOG -TO -
DIGITAL
CONVERTER
LMSD-288026
TO
MAGNETIC
TAPE
RECORDER
Fig. 7 'll Functional Diagram of Digital Record Electronics
7-47
LOCKHEED AIRCRAFT CORPORATION
MISSILES ortd SPACE DIVISION
mx:T
sL-N
Lai® 2SS025
and also reset tlx frame syne storage circuit to ihe "zero" state; thus, succeeding
conversion complete pulses do not change the magnetization of the tape until a now
composite frame sync pulse resets the frame sync storage to the "one" state.
The binary bits from the Dairac are delivered to the appropriate Digital Record Ampli¬
fier. The conversion complete pulse Interrogates these inputs and causes a change In
state of the magnsi lggtion of the tape if a "one" is presented to a Digital Record Ampli¬
fier and no change In state if a "zero" ia presented. Thus, the binary word from the
Dstrao, the composite frame sync, and the clock signal are all recorded on digital
tracks in parallel by the occurrence of a conversion complete pulse.
7. 2. 1 Frame Sync storage Ksssrd
The purpose of the frame Sync Storage Record is to convert composite frame sync
pulses from the Demultiplexer to pulees that will be accepted by the Frame Sync
Digital Record Amplifier ft should be remembered ihai information is recorded when
the input to a digital record amplifier is more negative than the negative threshold
level and a record pulse is received. Both of these conditions must be met for record¬
ing to be accomplished. The Frame Sync Storage Record is made up of an inverting
pulse amplifier and a flip-flop. A schematic diagram of the Frame Sync Storage
Record card ia shown In Fig. A-2S.
Positive composite frame sync pulses from the Demultiplexer appear at pin Z for
delivery to the inverting pulse amplifier composed of transistor Q1 and associated
components.
The negative-going leading edge of the output of the inverting pulse amplifier, which
is in time phase with the posits ve-gnlng i«>ding edge of the pulses at pin Z, is coupled
through capacitor C2 to turn off transistor Q3 of the flip-flop composed of transistors
Q3 and Q4 and associated components. This action causes the collector of transistor
Q4 to go negative, as well as the output of emitter follower composed of transistor Q5
and associated components which is delivered to pin K as output to the Frame Sync
Digital Record Amplifier.
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LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
LKHD-28&02S
Positive record puleee from the Pulse Amplifier appear at pin T for delivery to the
emitter follower composed of transistor Q2 and resistors R4 and HR. The emitter
follower output la differentiated by a network composed of capacitor €4, diode CR4.
and resistor K17 *o that the negative -going trailing edge of a pulse on pin T turns off
transistor Q4 of the flip-flop. The collector of transistor Q4 now goes positive as
does the output on pin K The delay of approximately one microsecond between the
positive-going leading edge of the record pulses, which clock out data from the Digital
Record Amplifiers, and the negative-going trailing edge of the record pulse, which
resets the ilip-flop, is necessary because data must be recorded before composite
frame sync Information is removed from the Frame Sync Digital Record Amplifier
input.
7. 2. 7. 2 Pulse Amplifier
The purpose of the Pulse Amplifier la u> convert conversion complete pulses from the
Datr&c to a form auitabie for docking out the data from the Digits! Record Amplifiers,
It le made up of an inverting pulse amplifier and a blocking oscillator. A schematic
diagram of the Pulso Amplifier is shown in Fig. A-26.
A conversion-complete pulse from the Datrac appears at pin M. where it enters the
Inverting pulse amplifier composed of transistor Q1 and associated components. The
negative-going leading edge of the inverting pulse amplifier output, which is in time
phase with the positive-going leading edge of the input pulse on pin M, is coupled
through capacitor C2 to fire the blocking oscillator composed of transistors Q2 and
Q3 and transformer Tl. Positive-going output pulses are delivered to pin T as a re¬
cord pulee to the Digital Record Amplifiers.
7. 2. 7. 3 Digital Record Amplifier
The purpose of the Digital Record Amplifier le to accept digital "ones" from the Datrac
and clock this Information onto the magnetic tape in NRZ form In phase with the record
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LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
L.MSU- 288025
pulses from the Pulse Amplifier. There is one Digital Record Amplifier for each
digital recording track. Thie circuit aieo provides sufficient power to operate the
recording heads. It ie made up of an inverting pulse amplifier, a flip-flop, two
itjn gates, and amplifiers and complementary emitter followers. A schematic dia¬
gram of a Digital Record Amplifier card la shown in Fig. A- 27.
Digital information appears at pin K in the form of rising and falling levels and Is
delivered to the inverting pulae amplifier composed of transistors Ol, 02, snd Q3,
diode CR1, and associated components. The operation of thin inverting pulse amplifier
is such that, for levela greater than approximately -11 volts. Its output la approxi¬
mately 0 volts. For levela leas than approximately -11 volts, lta output la approxi¬
mately +20 volts.
The output of the inverting pulse amplifier, which is the emitter ef transistor Q3, Is
delivered to two emitter followers, one composed of translator Q4 and resistor R13,
and the other composed of traneistor Q9 and resistor R24. The outputs of each emitter
follower are each ANDed with record pulses from the Pulse Amplifier, which appear
at pin T. These AND gates are composed of diodes CR3, CR4, and CR7, and diodes
CR5. CRB. and CR6.
The action of these AND gates causes the flip-flop composed of transistors Q6 and Q7
and associated components to change state whenever a binary "one" and a record pulse
are present at the same time. A binary "one" is an input level on pin K of less than
-11 volts.
A complementary emitter follower Is coupled to each side of the flip-flop through a
pulse amplifier. The collector of flip-flop transistor Q6 Is associated with the pulse
amplifier composed of transistors Q5 and Q14 and associated components and a com¬
plementary emitter follower composed of transistors Qll and Q13. The collector of
flip-flop transistor Q7 is associated with the pulae amplifier composed of tranaiatora
Q8 and Q15 and associated components and with the complementary emitter follower
composed of transistors Q10 and Q12.
7-50
LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
f'-'fcwf
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The output levels of the complementary emitter followers sre out of pb .se sad very
between approximately 0 and +10 volts. Resistor RSI serves to limit magnetic tape
recorder head current to approximately ICO ma at all times. The output to the
Magnetic Tape Recorder head is between pine a and c . An output monitor point of
the head current Is available at pin h .
7. 2. 8 Magnetic Tape Recorder
The Magnetic Tape Recorder is a special Ampex unit (FR-1100) that will aooept lt-tnch
or smaller reels of magnetic tape. It is designed to permit the recording of 11 track*
of digital data and four tracks of analog data on one-inch wide tape. Nine of the digital
tracks are used to record the digital words from the Dstrac. The remaining two digital
tracks are used to record the data sync pulse and the composite frame syne pulse. The
four analog tracks are used to record video, field strength, votes comment, and system
time signals. Normal operating Speed cf the recorder is ISO ips for Vifcrstfos data.
Distribution of tracks and the recording function for each track 1s as follows:
TRACK RECORDING FUNCTION
Digital
Bit 8
Bit 1
Bit 2
Bit 3
Bit 4
Data Sync
Bit 5
Bit 6
Bit 7
Bit 8
CompuaUe Frame Syuc
Analog
11
Video Backup
12
System Time
13
Spare (Range time at AMR)
14
Signal Strength and Voice
I
1.
■
L
7-51
I
LOCKHEED AIRCRAFT CORPORATION
MISSILES and SPACE DIVISION
LMeXi ztMQZr,
The theory of operation of the Magnetic Tape Recorder and the Procedure# for its
maintenance are described in detail In the instruction handbook Series FR-1100 Re-
eorder/aeproduoer - Magnetic Tape Recorders for Instrumentation, Ampex Corpora¬
tion, Redwood City, Calif, , i 4u! 195*, Special instructions for using this recorder
with the PAM-FM Ground Station are included in appropriate paragraphs in this
manual
7. 2. 8 Digital Reproduce Electronics
The Vibration Ground Station In the reproduce mode of operation is illustrated in
rig. 7-2.
The Digital Reproduce Electronics <Flg 7-1?) amplifies the dibits] signals from the
magnetic tape and temporarily stores and clocks the digital information into the
Datrao. Clock pulaes are delivered to the Datrac in the for"*' of a clear pulse and are
used to reset toe Deirac to a state corresponding to ail aero Inputs. Clock pulses and
the composite frame syne pulse are also delivered to the Demultiplexer.
Binary "ones" from the magnetic tape are amplified in the Digital Reproduce Ampli¬
fiers. Those binary "ones, 11 which represent the digital word and the composite
frame syno, are used to aet the storage circuits to the "one" state. Since no change
of state ia recorded on the magnetic tape for a binary "aero, " no signal is produced
for a "aero. " The binary "ones. " which represent the clock signal from the Digital
Reproduce Amplifier, are delivered through a delay circuit to the storage circuits
where they clock out the stored information In the storage circuits and reset the
storage olrcults to the "aero" state. Thus, binary "ones" representing digital, infor¬
mation are docked In parallel into the Datrac for conversion to analog form. The
effects of any static head skew and dynamic "jitter" of the tape axe reduced during
this process. Binary "ones'5 representing composite frame sync are clocked into the
Demultiplexer.
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LOCKHEED AUCKAFT COKPOtATION
MISSILES and SPACE DIVISION
Fig. 7-12 Functional Diagram of Distal ft^roduc* Electronic*
LMSD- 288026
¥li» dfclay otrcuit ha* three output*, each output oocurrlng l. 5 microseconds after
the other. However, the initial output \% delayed a suitable time to enable it to be
u*ed as a dock signal, but not so long that it beoomo* a part of the succeeding binary
wo*d. The first output 1* the clear pulse that la used to dear the Datrac. The second
oiilput, occurring 1, 5 microseconds later, le used as a dock pulse to the Demulti¬
plexer. The last output Is used as tha command pulse to the storage oiroults.
7. 2. 9. 1 Digital Reproduce Amplifier
The purpose of the Digital Reproduce Amplifier is to amplify the data from the digital
reproduce heeds of the Magnetic Tape Reoorder and to produoe appropriate data
pulses for the Date Storage and Gate circuitry which follows. A schematic diagram
of the Digital Reproduce Amplifier is shown in Fig. A-28.
The Digital Reproduce Amplifier contains a high- gain, four-stage, R-C coupled linear
amplifier; a linear phaae splitter, a full-wave rectifier; and an inverting pulse ampli¬
fier. Linear Circuitry is used until the data can be brought up to a voltage level that
ie kooeptable for pulse-type amplification. This is done so that the possibility of false
generation of output puisee by noise ie reduced to a minimum. A variable gain feature
is included so that operation with various tape speeds is possible.
Data from the Magnetic Tape Recorder reproduce heads appears at pin L for delivery
to the amplifier composed of transistors Q1 through Q5 and their associated com¬
ponents: This amplifier contain* four common-emitter stages in cascade and an emit¬
ter follower output stag*. A constant output level is maintained for various tape
speeds by varying tna gain. Gain is varied by the application of appropriate values
of resistance across pin* V and T . The resistances for this function are selected
by means of the TAPE SPEED COMPENSATION switch located on the Record and Re¬
produce Monitor Panel. Gain can also be varied by adjusting variable resistor R19.
Amplifier gain should be such that for any tape speed, output is S < *0. 5 ) volts peak-
to-peak.
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IOCKHKO AIRCRAFT CORPORATION MISSILES and SPACE DIVISION
LM3D-288025
The output of this amplifier Is delivered to the phase splitter composed of transistor
Q10 and resistors RIO and R43. Here, by adjusting variable resistor R43, two out¬
puts of equal magnitude and 180 degrees out of phase with respeot to each other are
delivered to separate diodes CR2 and CR3 of the full-wave rectifier, This rectifier
changes the positive and negative pulses of the phase splitter to a series of positive
pulses. These positive pulses are held between the levels of approximately o sod +a
volts.
One of the phase-splitter signals is transmitted through the emitter follower composed
of transistor Q» and resistor R38 for delivery to one side of the full-wave rectifier.
The other phase-splitter signal, which appears on ths emitter of transistor QIC, is
transmitted directly to the full-wave rectifier.
The foil-wave rectifier output pulses are delivered to the inverting pulse amplifier
at the base of the emitter follower oomposed of transistor Q7 and resistor R32.
Whenever the emitter-follower output goes positive, transistor Q8 is turned on and
its collector goes to ground potential. Whenever the emitter-follower output reaches
zero, or is negative, transistor Q8 is turned off and its collector goes to approximately
+13 volts. The signal which appears at the oolleotor of transistor Q8 is coupled
through the emitter follower oomposed of transistor Q6 and resistor R30 for delivery
to pin a as output to Data Storage and Gate.
Operation of the Digital Reproduce Amplifier 1b such that a negative-going output
pulse is generated whenever a data pulse appears across the input terminals,
7. 2. 9. 2 Data Storage and Gate
The purpose of the Data Storage and Gate is to hold the digital information received
from the Digital Reproduce Amplifier until all bits of information have been read out
of the Magnetic Tape Recorder, This delay is necessary to compensate for skew and
flutter in the Magnetic Tape Recorder. A command pulse clocks these bits into ths
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LOCKHEED AIRCRAFT CORPORATION MISSILES ond SPACE DIVISION
LMSD- 288025
Datrac for oonvaralon to analog voltaga. Each Data Storage and Gate card can ac-
oommodate two bits of information. A schematic diagram of thia unit ii ahown
Tig. A -28,
Two asperate hut identical circuits are present on each oard; each circuit stores one
bit of information until the oommand pulse transmits it to the following circuit. Each
circuit is made up of a blocking oscillator, a flip-flop, and an inverting pulse ampli¬
fier. Since all circuits are identical, only the operation of one circuit will be de¬
scribed.
Digital data from the Digital Reproduce Amplifier appears at pin K for delivery to
the inverting pulse amplifier composed of transistor Ql, diode CR1, and associated
components. If the level at pin K fails below approximately +9 volte, transistor Ql
is turned on, the collector of Ql goes to approximately +9 volts, and a positive-going
pulse appears at the Junction of aapacitor Cs and resistor R8. This positive pulse is
then coupled through capacitor C4 so that It turns off transistor Q2 of the flip-flop
composed of transistors Q2 and Q3 and associated components.
When a oommand pulse from Delay Command Pulse appears on pin T , transistor
Q5 ox ihs flip-flap will bo iu ITJvm wait amS change of state of the flip-flop causes the
collector of Q2 to go positive. The signal on the collector of translator Q2 is ooupled
through the emitter follower composed of transistor Q4 and resistor Rli' for delivery
to the blocking oscillator composed of transistors Q5 and Q6, transformer Tl, and
associated components.
If the level on pin K rises above approximately +9 volts, no pulse will be delivered
to the flip-flop end. consequently, no pulse will be available to fire the blocking
oscillator upon the arrival of a oommand pulse.
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LOCKHEED AIRCIAFT CORPORATION
MISSILES end SPACE DIVISION
LMSD- 288925
7. 2. 8. 3 Data Sync Delay Reproduce
The purpose of the Data Sync Delay Reproduoe is to delay the pulses from the data
sync Digital Reproduoe Amplifier sufficiently so that all information delivered from
the Digital Reproduce Amplifiers to the Data Storage and Gate gates has had time to
arrive before being docked out of the Data Storage and Gate gates into the Datrao.
It is made up of an inverting pulse amplifier and a one-shot. A schematic diagram
of the Data Sync Delay Reproduce card is shown in Fig. A-30.
Negative-going pulses from the data sync Digital Reproduce Amplifier appear at pin
a . These pulses are delivered to the inverting pulse amplifier composed of transis¬
tors Q1 and Q2 and associated components.
Positive-going pulses are coupled through capacitor Cl to the one-shot composed of
transistors Q3 and Q4. This one-shot is triggered by the negative-going leading edge
of the pulses at pin a . The one-shot output is fed through the emitter follower com¬
posed of transistor Q5 and resistor R15 and delivered to pin N as output to the Delay
Command Pulse.
A variable delay of from 4 to 25 microseconds la obtained by adjusting variable resis¬
tor R8. Its setting is adjusted so that the outputs from the following circuit, the
Delay Command Pulse, properly clock out the data contained in the Data Storage aid
Gate circuits,
7. Si; 8. 4 Delay Command Pulse
The purpose of the Delay Command Pulse is to provide dear pulses to the Datrao,
data sync to the Demultiplexer, and command pulses for the Date. Storage and Gate
cards during the reproduoe mode of operation. Delays of approximately 2 micro¬
seconds separate each of these pulses so that no interference can exist while gener¬
ating video, frame sync, and data sync. This circuit ia made up of three
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LOCKHEED AIRCRAFT CORFORATION
MISSILES and SPACE DIVISION
LMSD- 288025
oscillators, two of them with delay capabilities A schematic diagram of the Delay
Command Atlas circuit is shown in Fig, A-31,
Pulses from the Data Sync Delay Reproduoe enter at pin N and trigger the first block¬
ing oscillator composed cf transistors Q1 and Q2, transformer Tl, and associated
components, The positive-going portion of these pulses triggers this blocking oscil¬
lator. Output (which is essentially undelayed) leaves this blocking oscillator on pin
f for delivery to Datrac as the clear pulse. This output pulse, which is approximate¬
ly 2 microseconds wide, also passes into the delay and blocking oaclHator. The
negative-going portions of these pulses are extracted by capacitor Gfl, resistor RIO.
and diode CR3 and fire the blocking oscillator composed of transistors Q4 and Q5,
transformer T2, and associated components. Output from this oscillator is then
delivered to pin Z as data sync for delivery to the Demultiplexer. Output from this
blocking oscillator is also fed into a second delay and blocking oscillator circuit.
Again, the negative-going portions of the 2 -microsecond pulses are extracted by
capacitor C9, resistor R18, and diode CR5 and fire the blocking oscillator composed
of transistors Q7 and Q8, transformer T3, and associated components. Output of
this third blocking oscillator is delivered to pin T as a command pulse to the storage
cards.
Monitor points for the no. 1 and no. 3 outputs are at pins f and T respectively,
7. 2. 10 Dlgitai-to-Analog Converter
The Digital-to-Analog Converter is the same converter (Datrac) that la used for
analog-to-dlgital conversion, but operated in the digital-io-analog mode.
The Digltal-to-Analog Converter accepts the nine-bit digital words from the Digital
Reproduoe Electronics and reconstruct a the analog PAM composite pulse train. This
composite pulse train la then delivered to the Gate Driver Amplifier of the Base Band
Unit, which in turn delivers It to the Demultiplexer.
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LOCKHEED AiRCRAfT CORPORATION
MISSILES and SPACE DIVISION
LM8D- 28802ft
7. 2, 11 Base Band Unit, Reproduce Mode
In the reproduce mode of operation, only the Gate Driver Amplifier and the Reference
Amplifier portions of the Base Band Unit (Fig. 7-13) are uaed.
Input to the Reference Amplifier is from the Zero Data Seleotor In the Demultiplexer.
The Reference Amplifier output In the form of a d-o reference correction voltage Is
delivered by way of Jack J18 to grid 7 of vacuum tube VI in the Gate Driver Amplifier.
The Reference Amplifier functions in the same manner in the reproduce mode as It
does in the reoord mode.
The output of the Digital-to-Analog Converter In the form of an analog PAM composite
pulse train provides the second input at jack J14 to the Gate Driver Amplifier. The
output of the Gate Driver Amplifier is delivered to jack J17 as d-c video to the De¬
multiplexer. Except for the changes in Input, the Gate Driver Amplifier functions in
the same fashion in the reproduce mode as It does In the record mode.
7. 2. 12 Demultiplexer, Reproduce Mode
Although the Demultiplexer in the reproduce mode (Fig. 7-14) functions in much the
same way as it does in the record mode, inputs are from different sources and a part
of the synchronization logic in not used. Since clock pulses ana composite frame syne
pulses have been recorded, there is no need for a data sync generator, frame syno
generator, or a shift register. Two additional circuits are used in the reproduce
mode, however. These circuits are discussed In Paragraphs 7.2. 12. 1 and 7. 2. 12.2.
7.2.12.1 Duty Cycle!
Duty Cycle I is a chopper which converts the analog pulse train from the Datrao into
a serrated waveform (with a duty cycle of approximately SO percent) for delivery to
the analog data gates.
LOCKHEED AIRCRAFT CORPORATION
LMSD-288025
7-80
LOCKHEED AIKCIAET COtPOKATION
MISSILES and SPACE DIVISION
I
Fig. 7-13 Vibration Base Band Dnit. Reprodboe Mode
PAM DATA FROM ANALOG TO-tXGlTAL
CONVERTER VIA BASE BAND UNIT
LMSD- 288025
LMSD- 288025
This BO peroent duty factor enables the gain of the analog atgnal to visual display
equipment to be the same for record and reproduce modes. To prevent noise front
being fed to the Demultiplexer and display circuits, serrations are placed where
a minimum of switching noise will appear at the output of Duty Cycle I. Adjustment
of die duty factor of the data pulses is possible by adjuetmente on thte circuit. It
le composed of two one-shots, a flip-flop, and a keyed gate. A schematic diagram
of Duty Cycle I appears in Fig. A- 3 2.
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i
Positive data ayno pulses from the Reproduce Electronics appear at pin b for de¬
livery to one-shot no. I whloh Is composed of transistors Q1 and Q2 and associated
components. One output of one-shot no. 1 goes through the emitter follower composed
of transistor Q3 and resistor Rll and turns off transistor QB In the flip-flop composed
of transistors Q8 and Q9 and asaoolated components. The other output of one-shot
no. 1 passes through the emitter follower composed of transistor Q4 and resistor R12
and triggers one-shot no. 2 which is composed of transistors Q5 and Q6 and associ¬
ated components.
The output of one-shot no. 2 passes through the emitter follower composed of transis¬
tor Q7 and resistor R22 and turns off transistor Q8. When this occurs, output of the
emitter follower composed of translator Q10 and resiBtor R33 will go positive from
approximately -IS volts to approximately -5 volts. The output of the emitter follower
oomposed of translator Q10 and resistor R33 operates the inverting pulse amplifier
composed of transistor Qll and resistors R3S and R36 so that the signal at the junction
of resistors K37, R3S, and R59 will vary between +10 and -10 volts. 111686 pulses
will be out of phase with the output of emitter follower oomposed of transistors Q12
and Q15 and associated components. Video reproduce from the Gate Driver Amplifier
appears at pin Z and is switched on and off by the action of the keyed gats.
The output of the keyed gate Is delivered to pin H as serrated video to Data Gates.
This output will be at ground potential whenever the gate is not keyed, and will be at
data potential whenever the gate is keyed.
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The delay produced by both one-shot no. X and one-ahot no, 2 can be varied between
approximately 4 and 28 microaeoonda. Delay of one-ahot no. 1 la varied by adjusting
variable reelator R4; ita output determines when the keyed (ate a hall open. The
delay of one-shot no. 2 la varied by adjusting variable reelator R18, Ita output de¬
termines when the keyed gate shall close ,
7, 2. 12. 2 Frame Sync Delay Reproduce
The Frame Sync Delay Reproduce is a delay network to delay the composite frame syne
from the data sync pulses by approximately 5 to 10 mieroeeoonda. The composite
frame sync pulse la also transformed to the correct Impedance end amplitude for
driving the Demultiplexer. A schematic diagram at the Frame flyno Delay Reproduce
la shown in Fig. A-33. Since the circuit waa developed from the syne gate, the flip-
flop and one-ahot no. 2 as shown on the schematic are not used.
Composite frame sync pulses from the Digital Reproduoe Electronics appear on pin
Z . This positive pulse ia differentiated by capacitor Cl, diode CR1, and reelator R1
so that the positive-going portion of the pulses triggers the css-shot casspegsa of
transistors Q2 and Q4 and associated components . This one-ahot fires blocking oscil¬
lator no. 1 oomposed of translators Q6 and Q 7, transformer Tl, and associated com¬
ponents at a time several microaeoonda after foe initial arrival of the oorapoelte
frame sync pulse. This delay can be varied between 4 and 20 microseconds by adjust¬
ing resistor R3, but the delay la usually from 5 to 10 microseconds.
The positive-going output pulses of blocking oscillator no. l are delivered to dual
emitter follower oomposed of transistors Q9 and Qll and associated components. The
output level of the dual emitter follower ia seen at teat point TP1 and la adjusted by
variable resistor R28 to 10 ( * 2. 6 ) volts neak-to-peak.
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The gate composed of transistor Q18 end midari 8M . nd R37. which is normally
opeo, pea mo a positive pulse that Area blocking oscillator no. 8 oompossd of transla¬
tors Q18 and 914. transformer T8. sad associated components. The output of block¬
ing oscillator no. 8 la delivered to pin f as the delayed composite frame synoto ba
delivered to pin Z of the Sync Gate and to pin P of the Sync Selector.
7. 2. 18 Power Supply Interlock
The beelo purpose of the Power Supply Interlock is to prohibit the application of power
to any of the components of the PAM- PM Ground Station unless power from all four of
the power supplies is present simultaneously. Other functions of this unit sro:
(1) to provide a time delay between dm application of heater power and plate volt- ge
to the Base Band Unit; (2) to provide a means of distributing power to unite; and
(S) to route various record/ reproduce. Magnetic Tape Recorder Interlock, and G-A/
Vibration relay signals between major components in the Ground Station.
The Power Supply Interlock Is composed of 15 relays (two of which are one-minute,
thermal-delay relays), a il5-vwii-ac isolation transformer which provides power for
the 115 -volt relays, and various connectors.
attention should be given the schematic diagram shown in Fig. A-34 ms all
controlling signals, their origins and destinations, and the routes of incoming and
outgoing power cable* are clearly labeled.
7. 2. 14 Relay Beard
The purpos* of the Relay Board Is to make it possible to shift quickly between record
and reproduce modes of Ground Station operation. Several circuit rearrangements
»wwwig the component boards In the Demultiplexer and other units are required when
station modes are swltnhed. In the Demultiplexer, several cards with three DPDT
relays each provide the necessary switching. For example, switching between the
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Sync Separators and the Sync Reproduce electronics, or between the Duty Cycle and
the Base Band Unit, are all accomplished with Relay Boards, which are in turn driven
by the Reoord/Reproduce controls of the Monitor Panel. A schematic diagram of the
Relay Board la shown In Fig. A-35,
T. 2. 15 Main Monitor Panel
The functioning ol main and mb monitor panels as a m urns of applying "scope probes"
rapidly to critical points in the Ground Station is documented in Volume I and in
Section 11 of this volume, it should be pointed out that the main monitor panel also
performs, by means of nine DPDT relays, most of the switching necessary to change
p. Ground Station between G-A and Vibration operation. Also, control signals for
POWER ON-OFF, RECORD- RE PRODUCE, and G-A VIBRATION are Initiated by a
series of push buttons on die Monitor Panel. A schematic diagram of die Monitor
Panel is shown in Fig. A-36.
7. 2. 16 Signal Strength and Voice Record and Reproduce Filters
The purpose of the Signal Strength and Voice Record and Reproduce Filters is to
combine the receiver signal strength output and the voice signal for recording with
FM record electronics and to separate the two signals on reproduce. This is done
with simple passive filters and a resistive adder which limits the frequency re¬
sponse of the recorded signal strength from dc to approximately 100 cps and the
voice signal from approximately 300 epe to 10 kc. A schematic diagram is in
Fig. A-37.
Revised 25 May 1960
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7. 3 G-A
7. 3. 1 Receiver
Input to the G-A Ground Station is received at a modified Nems- Clarke 1412 Telemetry
Receiver as a PAM-FM signal. After the FM signal has been demodulated, three
signals are delivered to other equipment at the station. A dc- coupled PAM signal
is delivered to the Base Band Unit at an average level of approximately +6 volts. A
field strength signal is delivered directly from the receiver to the FM electronics
of the Magnetic Tape Recorder for recording on an analog track. An ac- coupled
signal, to be used as a backup for the digital recording, is delivered through an
auxiliary jack to the analog electronics of the Magnetic Tape Recorder for recording
on an analog track. The modifications to the Nems- Clarke 1412 Telemetry Receiver
provide a dc- coupled output near ground potential and were made to achieve com¬
patibility with the PAM-FM Ground Station in tile following manner:
e To provide dc~coupled and ac- coupled video with the phase
opposite to that provided by the unmodified receiver
e To provide video with a level independent of any readily
accessible adjustment
The modifications were accomplished by bypassing the video amplifier and obtaining
an output signal directly from the cathode of the FM discriminator amplifier (V101).
A schematic diagram of the modifications is shown in Fig. A-l. Theory of operation
and operating and maintenance procedures are described in Instruction Manual for
Model 1412 Telemetry Receiver, Nems-Clarke, Inc., Silver Spring, Maryland.
7. 3. 2 Base Band Unit, Record Mode
The purpose of the Base Band Unit is to
e Amplify the signal from the receiver and provide three separate
output signals, each of a different level and isolated from one another
Revised 25 May 1960
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• Insert correct d-c reference level into two of the three output
signals
e Litni the bandwidth of the PAM output signals without
introducing excessive crosstalk
A block diagram of the G-A Base Band Unit in the record mode is shown in Fig, 7-15,
The three output signals of the Base Band Unit are (1) a 19-volt peak-to-peak signal
for the Datrae, (2) a 7-volt peak-to-peak signal for the Demultiplexer data gates,
and (3) a 15- volt peak-to-peak signal for the Demultiplexer sync circuits.
The 18- volt peak-to-peak signal for the Datrae must be referenced eo that the
minimum peak is -9. 5 volts. The 7-volt peak-to-peak signal for the data gates is
referenced so that zero output of the interpolation filters of the display circuitry
corresponds to zero data, i. e. , the minimum peak is approximately -1. 5 volts. The
15-volt peak-to-peak signal for the sync circuits is not referenced and is a-c
coupled.
Since the G-A PAM signal Is a 16-kc pulse repetition rate, it can be considered
a relatively low-speed system.
The video output of the receiver is followed by a noise filter which limits the bandwidth
to that required to pass the PAM signal and removes the excess noise. The
characteristics of the noise filter are determined by the total sampling rate, the overall
system accuracy, and the allowable crosstalk between successive samples. For the
G-A Ground Station, an R-C fll'ar is sufficient to accomplish this purpose.
Two signals flow through the Base Band Unit. Che is the PAM pulse train, the other
is the d-c reference feedback correction voltage that is derived from a portion of
the pulse train.
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Fig. 7-15 G-A Base Bend Unit, Record Mode
LMSD 2B8025
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amplitude. intari tha DC Amplifier where it i« amplified approximately 10 times
without being Inverted. Thia amplifier is composed of direct-coupled circuits.
A suitable means of offsetting positive bias voltage from the receiver is included.
The output of the DC Amplifier, which is now at a level of approximately 14 volts
peakio-pcak, is fed Into the Noise Filter, a single- pole, R-C section. Here, the
signai-to-noiae ratio of the PAM pulse train la improved without the Introduction
of excessive crosstalk and approximately S volte of negative offset voltage are added
to the output signal.
Thia signal is delivered to the K>ise Filter Amplifier at a level of approximately
4 volts because of attenuation In the Noiae Filter. The signal Is then amplified bo
that the Noise Filter Amplifier output to the Datrac is IB volts peak-to-peak.
An adjustment, called the Overall Gain, is involved In this amplifier to achieve the
desired amplification. An additional adjustment to correct the d-c level to -9 (± 0. 25)
volts is also included in th ' Noise Filter Amplifier. This signal which is delivered
to the Datrac can be routed through the Reference Voltage Optional Clamp circuit
If the Demultiplexer should fail to deliver the correct d-c reference voltage.
At this point In the signal flow of the Base Band Unit, the PAM pulse train Is divided
into three outputs. One output is the 19-volt peak-to-peak signal to the Datrac,
another is the 15-volt peak-to-peak signal to the Demultiplexer sync circuits, and
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The Gate Driver Amplifier is used to attenuate the 19-volt peak-to-peak signal to a
7-volt signal and supply a low a our os impedance to drive the data gates. A d-c offset
adjustment is incorporated to adjust the minimum peak (sync interval) to approximately
-1.5 volts. Incorporated In the Gate Driver Amplifier is a relay activated by the
Record-Reproduce switch in the Monitor Panel so that the input to the data gates by
way of the Gate Driver Amplifier can be routed from the Datrac or the Noise Filter
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Amplifier, depending on the mode of Qp*r*ilott =
The d-c reference correction voltage originates in the Demultiplexer where the sync
interval is sampled by the DC Reference Filter Board and smoothed through a i-kc
low-pass filter. ThiB signal is then delivered to the Reference Amplifier of the Base
Band Unit where the d-c error voltage is amplified approximately 50C times and delivered
to a single-pole, R-C section, low-pass filter with a cutoff frequency of 2 cps. This
filter is physically located in the Gate Driver Amplifier. The d-c correction voltage
is switched by a relay In the Gate Driver Amplifier to a differential input of the DC
Amplifier in the record mode or to a differential Input of the Gate Driver Amplifier in
the reproduce mode.
7. 3. 2.1 DC Amplifier
The purpose of the DC Amplifier is to amplify the Incoming PAM signal approximately
10 times and establish a d-c reference level of approximately -2 (±2) volts. These
functions are performed by using three dual triode (6201) vacuum tubes and their
associated components. The first two cathode- coupled tried** (VI and V8) act as a
comparison amplifier that amplifies the difference of the signals appearing on grids 2
and 7 of VI. The third cathode- coupled dual triode <V3) acts as a parallel cathode
follower and furnishes a low output Impedance to the Noise Filter. Zener Diodes are
used to correct the d-c offset throughout the Amplifier. A schematic diagram of the
DC Amplifier is shown in Fig. A-2.
Two inputs to the DC Amplifier are provided. One input is the PAM pulse train
from the receiver: the second is the d-o reference level from die second low- pass
filter in the d-c reference feedback loop.
The PAM signal from the receiver is picked up at jack J4 at a level of approximately
-td volts dc. It is passed through Zener coupling diode CR7 where the level la reduoed
to approximately zero volts dc. This signal la then applied to grid 2 of VIA. At
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the «ame time, the signal input from the Reference Amplifier, by way of the second
low-pass filter, is applied to grid 7 of V1B by way of a network composed of
resistors R9, RIO, and Rll.
In order to exercise adequate control over the d-c offset voltage, it is necessary
to balance the plate current being ap died to VIA and V1B, the firot stage of the
amplifier. This is accomplished by means of potentiometer R2 (DC Balance no. 1).
While this adjustment la being made at R2. the input from the Reference Amplifier is
disconnected at jack J5. Resistor R2 is adjusted so that the sync Interval (absence
of a data pulse) is approximately -2 ( ± 2) volts dc as. observed at test point TP3.
The output of V1B is passed through an offset voltage control network composed of
diodes CR1, CR2, and CR3 which reduces the d-c voltage by 180 volts ( - 10 percent).
The signal is then applied to grid 2 of V2A. The cathode of V2A Is coupled to the
cathode of V2B, which Is next to receive the signal. At the same time, there appears
on grid 7 of V2B the signal from the output of VS, a part of the amplifier's Internal
feedback circuit.
The output from the plate of V2B is passed through a second offset voltage control
network composed of diodes CR4. CR5, and CR6 which reduces the d- c voltage by
180 volts ( llO percent). Capacitors C2 and C3 are used to suppress the high-
frequency noise generated in the two Zener diode strings CR1, CR2, and CR3;
and CR4, CR5, and CR6.
7 ) signal is then applied in parallel to grids 2 and 7 of V3A and V3B, the parallel
& ode follower. The output of this parallel cathode follower is delivered
through jack J6 to the Noise Filter. At the same time, this output is fed back to the
grid? of V2B and V1B by means of the feedback resistors R9, RIO, R15, and R16.
Feedback resistors R9 and RIO are used to control the overall gain of the DC
Amplifier to approximately 10.
There are three teat points in the DC Amplifier. Test point TP1 provides a
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bhi up ling point for the input from the receiver after passing through *he 6-volt
Zener diode CK7. Test point TP2 provides a sampling point for the input from the
Reierenee Amplifier. Test point TP3 provides a sampling point for the output of She
DC Amplifier. The input from the receiver, after passing through the 6-volt
Zener diode CR7, is also delivered to the Monitor Panel through Jack J1 an the
RCVR VIDEO DC position on Switch A and Switch B.
A jumper between Jacks J2 and J3 is normally used with the DC Amplifier.
Should an occasion arise when operation with the composite pulse train from some
source other than the receiver is desired, however, the Jumper could be removed
and the input applied to jack J2.
7.. 3. 2. 2 Noise Filter
The purpose of the Noise Filter Is to improve the signal- to-noise ratio of the
composite pulse train without introducing excessive crosstalk. It is composed of
a time delay circuit, a summing junction, a d-c offset- adjustment circuit, and an
output circuit . Internal switching and separate plug-in output circuits permit use with
both Vibration and G-A Ground Stations. Input to use Noise Filter iroin the DC
Amplifier is at jack J7 and its output to the Noise Filter Amplifier is at jack J8. A
schematic diagram of the Noise Filter, including circuits used in both Vibration
and G-A operation, is shown in Fig. A-3.
With the SYSTEM switch on the Monitor Panel set at the G-A position and a G-A
plug-in unit in place, all Noise Filter components needed in the G-A system are in
operation. In G-A operation, the Noise Filter is a single-pole, R-C section with
a cutoff frequency of 2. 2 times the sampling rate, or about 35 kc. No adjustment
of the delay attenuator or tuning capacitor controls is required with the Noise
Filter in the G-A mode of operation, because no delays or tuned circuits are used;
both the time delay and summing junction circuits are inoperative. Bandlimlting
of the composite pulse train is accomplished with the R-C filter alone, and the
Revised 25 May 1960
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resulting crosstalk Is bald to a tolerable level.
The signal ia delivered through resistors R2 and R3 to both grids 3 and 8 of
tube VI which acts as a parallel cathode follower. Output to the R-C filter Is
delivered to the junction of resistors R7 and R8, and output to the Noise Filter
Amplifier is the voltage developed across crpacltor C2 of the plug-in unit.
D-C offset adjustment is accomplished by a circuit composed of tube V2 and
its associated components. By varying the operating point of V2 with the DC
Offset no. 1 control, resistor R13, d-c current flowing out of the junction of
resistors R7 and R8 can be changed, and the resulting I-R drop becomes offset
voltage. This adjustment is made so that there Is 3. 5 (1 0. 5) volts offset be¬
tween jacks J7 and Jo. Offset conditions should always be checked when changing
from one system (Vibration or G-A) to the other.
7. 3. 2. 3 Noise Filter Amplifier
The purpose of the Noise Filter Amplifier is to amplify the signal delivered by
the Noise Filter so that the peak- to- peak voltage with full modulation is 18 (i 1)
volts. The signal level must be such that the sync level (absence of data pulse)
is -9. 5 (t 0. 25) volts. These functions are performed by using two 6201 dual-trlode
vacuum tubes and one 6463 dual-trlode vacuum tube, and their associated components.
The first two cathode- coupled trlodes (VI and V2) act as a comparison amplifier
that amplifies the difference of the signals appearing on grids 2 and 7 of VI. The
third cathode- coupled triode (V3) acts as a parallel cathode follower and furnishes
a low output impedance. Zener diodes are used to correct the d-c offset throughout
the amplifier. A schematic diagram of the Noise Filter Amplifier is shown in
Fig. A-4.
The signal is delivered to the Noise Filter Amplifier at jack ,J9 and applied to
grid 2 of VI. At the same time, the signal appears at grid 7 of VI as feedback from
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cathode follower V3. Plate current to VI la balanced by means of DC Balance
no. 2. In order to make this adjustment, It Is necessary to disconnect the Input
signal at Jack J9. Test point TP3 should go to ground potential when the adjustment
is properly made.
The output of plate 6 of VI is delivered to grid 2 of V2, the second cathode-
coupled dual trlode, through an offset voltage conti ol network composed of diodes
CRl. CR2. and CR3 which reduces the d-c voltage by 180 volts ( - 10 percent).
Cathode 2 of V2 Id coupled to cathode 8, which is next to receive the signal. At
the same time, the signal from the output of V3, a part of the amplifier feedback
circuit, appears on grid 7 of V2.
The output from plate 6 of V2 is passed through a second offset voltage control
network composed of diodes CR4, CR5, and CR6 which reduces the d-c voltage by
180 volts ( 1 10 percent). Capacitors Cl and C2 are used to suppress the high-
frequency noise generated In the two Zener diode strings.
The signal is then applied to grid 3 of cathode follower v'3. The uuipui of this half
of V3 appears on cathode 2. This output is delivered to grid 7 of V2 and grid 7
of VI through resistors R7, R8, R9, and R13 which act as voltage dividers of
a feedback circuit within the Noise Filter Amplifier. This output is also coupled
to jacks Jll and J12. At the same time, a part of this output is delivered to
grid 8 of V3 through resistor R17 and variable resistor R18. 'he output of this
half of V3 appears on cathode 7 and is ac- coupled to the Sync Separator the
Demultiplexer through jack J10. Capacitor C4 acts as a blocking capacitor to
prevent high voltage from entering the Demultiplexer.
There are two adjusting points in this circuit in addition to DC Balance no. 2,
which was described earlier. Both of these points, resistors R8 and R18, are
adjusted with the input from the Noise Filter connected to jack J9. Resistor R8
(O erall Gain) is set so that the peak-tc-peak voltage with full modulation is
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IMSU 2n»d02
19 (* 1) volts at test point TPS. it is advisable to recheek the adjustment of
DC Balance no. 2 after resistor Rfl is adjusted to assure that ground potent a 1 is
present without signal input. Variable resistor UiS (a-c gain) is adjusted so that
the peak-to-peak voltage with full modulation is 15 ( * 2) volts nl test point TP7.
The output at Jack Jll is connected to the Reference Voltage Optional Clamp where
a switch delivers the signal directly to the Datrac and the Gate Driver Amplifier
or may be clomped to a a-c reference voltage before delivery to the Datrac and Gate
Driver Amplifier.
There are three test points In the Noise Filter Amplifier. Test point TP6 furnishes
a sampling point for the- input from the Noise Filler: test point TP7 furnishes a
sampling point to the a-c video output to the Demultiplexer; and test point TP8
furnishes a sampling point to the d-c video output to the Reference V age Optional
Clamp.
The Noise Filter Amplifier has three outputs. One output is delivered to the
do -coupled Analog-to-Digital Converter. The signs! !s also fed rtc coupled to the
sync circuits in the Demultiplexer. Peak-to-peak amplitude of this signal is
15 ( ± 2) volts. The third output of this unit, which is identical to the output going
to the Analog-to-Dlgltal Converter, is delivered to the Gate Driver Amplifier.
7. 3, 2. 4 Reference Voltage Optional Clamp
An optional Clamp circuit is included in all Vibration and G-A Ground Stations with
record capabilities. The purpose of the Clamp is to increase the reliability of the
station in the record mode by allowing the operator an optional method of restoring
the correct d-c record level in case the main d-c correction circuit fails. A
schematic diagram of the Reference Voltage Cfctlonal Clamp is in Fig. A- 5.
The Clamp circuit is contained in a 2-3/4 in. by 2 in. box that is mounted on top
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of the case containing the Reference Amplifier In the Base Band Unit. The switch
position on the clamp box is labeled CLAMP - SERVO. When the switch Is in the
SERVO position, the clamp is eliminated from the circuit, and the reference level
is furnished by the d-c correction circuit. When the switch is in the CLAMP position,
the d-c correction circuit is eliminated and the clamp furnishes the appropriate
d-c correction level.
The clamp level ta fixed at -9 ( - 0. 5) volts by an SV-9 Zener diode. In order
that the d-c record levels remain approximately the same for the CLAMP or
SERVO positions, the main d-c correction circuit must be set up to match the
clamp level.
7. 3. 2. 5 Gate Driver Amplifier
The Gate Driver Amplifier furnishes a gain factor of approximately 0. 33 and a
d-c voltage offset so that a zero signal at the vehicle multiplexer results in a zero
signal at the output of the Demultiplexer. This unit delivers the signal to the
Demultiplexer.
This amplifier is made up of a comparison amplifier, a positive peak limiter, a
cathode follower, an offset control, and an output clipper. To facilitate switching
between the record and reproduce modes of operation, the Reference Amplifier
low-pasa filter is Included as a part of the Gate Driver Amplifier. A schematic
diagram of this circuit is shown In Fig. A-6.
In the record mode of operation, either the Reference Voltage Optional Clamp or the
Noise Filter Amplifier furnishes the Input to the Gate Driver Amplifier. In the
reproduce mode of operation, the Datrac furnishes the input to the Gate Driver
Amplifier. The input signal appears at jacks J13 or J14, depending on the mode of
operation, and is delivered to grid 2 of VI (a dual-triode vacuum tube 6201 which
acts as a cathode- coupled comparison amplifier) through the resistors Rl, R2,
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and R3 which serve as a voltage divider and attenuator. The output of plate; 6 of
VI is passed through diode CR1 for offset voltage control, causing the voltage to
drop 180 volts ( 1 10 percent). Capacitor C3 suppresses the high- frequency noise
generated by diode CR1. The signal la then passed through the positive peak
limiter, composed of variable resistor R13 (limiter bias), diode CR2, and
capacitor C4, and is delivered in parallel to grids 3 and 8 of cathode follower V2,
a 6463 dual-triode vacuum tube. The output of V2 (cathodes 2 and 7) Is passed
through a voltage offset adjustment network composed of diodes GR3, CR4, and
resistor R18 (DC Offset no. 2). The signal is then delivered to jack J17 through
an output clipper composed of diodes CR5 and CR7. This clipper prevents the
output to jack J17 from going beyond +10 or "5. 6 volts.
Also included in the Gate Driver Amplifier is she second low-pass filter for the
d-c reference feedback loop. This filter consists of resistor H4 and capacitors
Cl and C2. Input to the filter is from the Reference Amplifier. In the record mode
of operation, the filter output is delivered to the differential input of the DC Amplifier.
In the reproduce mode of operation, since the DC Amplifier is not used in this
mode, the filter output is delivered to the differential input (grid 7 of VI) of the Gate
Driver Amplifier through resistors Rll and R14. This unit filters out unwanted
frequencies and prevents hunting.
7. 3. 2. 6 Reference Amplifier
The Reference Amplifier has a variable gain from 10 to 2500 to amplify die d-c
correction feedback voltage. A gain of 500 is normally used during operation of
the Ground Station in the G-A mode. The output is delivered first to the second
lov-pasB filter contained in the Gate Driver Amplifier and then to the differential
input of the DC Amplifier in the record mode of operation, or to the Gate Driver
Amplifier in the reproduce mode of operation.
The circuitry of this amplifier is described in detail in the Handbook of Operating
Revised 25 May I960
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gad Maintenance Instructions, A- 12 DC Amplifier, supplied with the Ground station.
A schematic diagram of the amplifier la shown in Fig. A- 7, Sheets 1 through 3.
The input to the Reference Amplifier la of a differential type with respect to ground
in order to reduce ground loop problems. This input from the DC Reference Filter
Board in the Demultiplexer appears at jack J25 at approximately 0 volte (within a
few millivolts) when the feedback loop is closed. If instability of the video base
line is noted, the gain should be reduced until stability is achieved. This instability
will be noted at test point TP11 in the Gate Driver Amplifier. Random noise may
be present, but it is filtered out by the low-pass filter In the Gate Driver Amplifier.
The output at jack J23 should be 0 ( ± 5) volts and must never exceed * 10 volts
as this level would represent lose of operation of the d-c reference feedback loop.
Although no damage to the equipment would result with the output approaching
these limits of - 10 volts, data recovery accuracy of the Ground Station would
suffer appreciably.
7. 3. 3 Demultiplexer, Record Mode
A functional diagram of the G-A Demultiplexer in the record mode of operation is
shown in Fig. 7-16. The three principal functions of the Demultiplexer are:
(1) to separate the data sync pulse from the composite data signal for use as a
clock pulse for the Demultiplexer and the Analog-to-Digital Converter (Datrac)
and to generate frame sync pulses from the composite data signal; (2) to supply
keying signals for the Sample and Hold circuitry; and (3) to sample the sync Interval
that appears on Channels 1 and 9 and send it through a high- gain Reference Amplifier
in the Base Band Unit as a d-c correction voltage fed into the differential DC
Amplifier.
Since the Ground Station is slaved to the vehicle dock, a clock signal must be
recovered from the composite pulse train. This is done In the data sync generator
wher e a pulse Is generated for every analog pulse and sync interval in the PAM
Revised 25 May 1860 7-79
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LMSD-288025
pulse train. The phasing can be controlled to give the appropriate time relation
between the clock signal thus generated and the analog data pulses from the Btst
Band Unit,
One output of the data sync generator is used to drive the binary countdown that pro¬
duces the square-wave signals used for "ANDing*' purposes In the matrices. The
output of the matrices are keying signals for the analog data gates and the Sample and
Hold Circuit* which receive their Input in the form of the PAM analog pulse train
from the Gate Driver Amplifier in the Base Band Unit. These sequential keying sig¬
nals to the analog data gates are on separate lines and are connected to the appropriate
analog data gates which open and close In correspondence with the keying signals.
The "on” time of any one high-frequency data gate Is the clock period, or 63. S
microseconds. The "off* time is one frame minus the clock period, or 193?. ft
microseconds. The "on" time for a subcommutated data gate Is the same as die "on"
time for a high-frequency data gate, or 62. ft microseconds. The "off" time of die
subcommutated data gate is eight frames minus one clock period, or IS, 937. ft
microseconds.
To keep the Demultiplexer in synchronization with the PAM pulsa train (i.s. , to open
analog data gate no. 1 when each channel of the PAM pulse train la delivered from
the Base Band Unit), a frame synchronization pulse is used. Frame synchronisation
pulses are generated in the frame sync generator which produces a pulse whenever
a pulse is missing in the PAM pulse train. To ensure that this pulse Is a valid
sync pulse and not a stray pulse as might be generated in the presence of r-f nolso
Interference or a faulty multiplexer, a certain amount of logic la incorporated into
the circuitry.
Frame sync occurs on Channels 1 and 9. Therefore, any potential syno pulse is
delayed exactly eight channels by means of an eight -bit shift register and compared
in a logic gate with other potential frame sync pulses being generated. This will
produce a frame sync pulse output only when missing pulses occur exactly eight
channels apart This provides protection against the generation of spurious frame
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syao palm by faulty date puliw. One* apparent frame aync has been established,
a ante get# <> triggered, which c pens to receive a sync puiae only amen one le
expected aa determined by the hlgs-trequeccy binary countdown and matrix. When
u>e sync pole# arrives, it ohaeee the gate and blocks any apurioue pulses. If the
sg m puM dose not arrive aa expected, the aync (ate remalna open until eyno is
again established. This logic performs the function of blocking periodic and
nonperiodic false aync pulses as well aa the suboommutated sync pulse, which
appears aa a nonperiodic sync pulse to the high-frequency binary countdown.
Soboomrautste frame sync occurs on Channel 92. Therefore, the train of potential
sync pulses la delayed exactly one channel by a one-bit shift register and compared
In a logic gate with potential frame sync pulses being generated by die Frame dyne
Separator. This will produce a frame aync pulse output only when missing pulses
occur exactly one channel apart. These pulses are fed into a keyed gate that is
triggered by die Channel 1 keying pulse from tile matrix. Thus, after the maln-
ohsnnel pulse sequencer has been synchronised, die keyed gate allows subcommutated
sync pulses to pass through die keyed gate only during Channel 1 time. The output
of die keyed gate is delivered to a subcommutated sync gate which operates in the
same fashion as the high-frequency gates except that it is controlled by die sub-
commutated countdown and matrix.
The two signals appearing at die input of the high-frequency and subcommutated
sync gates are delivered to the Digital Record Electronics for recording on a
digital track. These signals are combined into one line by means of an OR gate.
7. 3. 8. 1 Data Sync Separator
The purpose of die Data Sync Separator is to extract data sync and clock information
from die composite pulse train (a-c video). The Data Sync Separator la composed
of die following circuits: clamp and clipper, band -pass filter, pulse shaper,
clipper amplifiers, one-shot, emitter follower, and blocking oscillator. (For a
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schemat ir diagram, aee Fig. A-38). Clock output occurs in the form of a square
wave or pulaes ; data sync is in the form of pulses only. Clock information is in
time phase with data sync information. Data sync output is actually dock Informa¬
tion which has been delayed so that keying pulses for the data gates occur at a
time when inter channel crosstalk is at a minimum. The Q of the bend-pass
filter is such that clock and data sync outputs are present when as many as
approximately 30 consecutive data pulaes are missing. Operation of the Deta
Sync Separator oaaaea whenever more than approximately 30 consecutive data pulses
are missing.
The composite pulse train input (a-c video) from the Noise Filter Amplifier
appears at pin J. It then enters the clamp and clipper circuit, which la composed
of diodes CK3 and CR4, transistors Q3 and Q6, and associated components. Ibis
circuit restores the d-c level to the a-c video and clips it below minimum data level.
Resistor R13 is adjusted so that positive peak dipping occurs at minimum data
level, 1. 5 (i 2) volts. Test point TP1 - the junction of diode CR4 and resistor
R43- should be observed when this adjustment is being made.
The output from the clamp and dipper circuit passes through the emitter follower
composed of transistor Q6 and reals tor R19 into toe b md-pass filter. This bund-pass
filter is a ringing, oscillator-type circuit in which toe resonant frequency- is tout
of the sampling rate of toe composite pulse train. The output level control of the
clamp- and- cupper circuit resistor tua is adjusted so mat toe peak-w-pe**
amplitude of toe output sine wave at the Junction of capacitor C14 and diode CXI
is 15 ( - l) volts. Fine tuning of the tank circuit is mads by adjusting capacitor
C13A.
The signal is coupled into the pulse shaping network through capacitor Cl 4.
Translators Q14 and Q17, diode CR7, and associated components are a dual
emitter follower and damp dreuit. Its output is fed into the clipper circuit
composed of diodes CR9 and CR10, translator Q19, and associated components.
Revised 25 May I960 7-83
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BlUooa dlodii CR9 and CRIO change the tine wave from die dual emitter follower
Into an approximately square wave.
Ifeie square wave Is coupled into the clipper amplifiers through the emitter
follower transistor CU9 and resistor R52. There are two satirating-type amplifier
stages sod two emitter follower stages in die clipper amplifier circuitry. The
two amplifiers are transistors Q2 and Q7 with their associated components; the
two emitter follower stages are transistors ( i and Q 9 with their associated
components. The signal la amplified but not inverted, and the output la fed into
four succeeding emitter follower* in parallel. Output of the clipper amplifiers,
which is now * square wave, passes through the emitter follower transistor Q8
and assoeltueu components to pin II and through the emitter follower transistor
Q10 and associated components to pin R. These two clipper amplifier output* are
then delivered as a clock square wave to the eight-bit shift register (pin M) and to the
frame sync separator (pin R). Output of die dipper mpliflers is also fed to a one
•hot through die emitter follower transistor Q12 and jsodated components.
Positive- goto* part' < of the square wave trigger the one-shot, which is composed
of transhuuM a QIC uno Q18 and associated components. The variable delay of
approximately 4 to 25 microseconds la adjusted by resistor R39 in such a manner
that the data gates are keyed when minimum Interchannel crosstalk occurs. One-
shot output (monitor. die junction of capacitor C21 and resistor R51) is a
series of positive pulses. These pulses firs • blocking oscillator composed of
transistors Q13 and Q16, transformer Tl, and associated components. Output
of the blocking oscillator consists of data sync pulses which are fed to the pulse
sequencer and frequency divider at pin b. Finally, the output from the clipper
amplifiers passes through emitter follower composed of transistor Q1 end associated
components, differentiating circuit capacitor C4, diode CR2, resistor R8, emitter
follower translator Q4, and associated components to pin T. This output is then
delivered as a aeries of positive clock pulses to the Data Sync Relay Record.
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LMSD-383CS5
7.3.3. 3 Frame Sync Separator
The Frame Sync Separator produoee a pulae wheoover a data pulae ta absent in the
oompoalte pulae train. This unit la adjusted ao that whenever *»>* level of a data
pulae falls below a 0. 5-volt level with reference to the base tins, a pulae la produced.
The unit ta made up of the following fu£ ottering olrouite: d-o reatorer, poaltlve path
clipper, adder, decision level Inverting amplifier, one abet, and three btoddng
oaolllatora. (For aehematle diagram aea Fig. A-55.)
Tha oompoalte pulae train (a-e video) Input la delivered to pin J. It la ten elampnd
to a few tenths of a volt, positive d-o, by means of the d-o restorer oompoaed of
capacitors Cl and C4, diode CHS, diode CR11, and resietor SB.
The signal la than delivered to the positive peak clipper set to clip below wlnlmnWi
data level, which is approximately -ft volte a* monitored a: teat point TF1. His.
dipper la oompoaed of translator Qi, diode CSS, and asaoc'ateu components. ifca
clipping level la adjuated by varying resistor R8. ,
Clock square wave from the Data Sync Separator appears at pin B. It ladeltvetddto
v* '
the dock blocking oscillator oompoaed of transistors QB and ^1,
and anaodated components. The output of £hls b’ockteg oscillator la
pin S as reset pulses to the gtght-ftit Shift Racists?, ft also *s »:• ik¬
ons -shot oompoaed of translators QS and Q9 and asaodatod oomponguta. This
multivibrator introduces a variable time delay from 4 to SB microseconds. 1 Ip
time delay is set by adjusting resistor RUB. The output Is delivered sa
to a delayed blocking oscillator composed of transistors Q10 and QH*
T3, and asscoUtod oomponents.
The output of this blocking oscillator ia delivered to th
sistor RIO. This adder combines the dipped oompoalte pulse train and delated data
sync. Resietor ROB in te one-shot circuit is adjusted so tel the I
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LM8D-2S802B
MocUsg oscillator pul— s (Fig. 8-3) ar« centered on tbe data pul— ■ aa they ara
monitored at tost point TP3.
Ttm output of the adris-t is delivered to live dedr ion lavsl Inverting ampliflar com¬
posed of transistors Q2 wk' Q3, dlotla CRR. ana assorts tod components. This
atopHOer — toots too blocking o* dilator puUre which coincide with the abaenoe of
data pulses and provides? a positive -going puite to fire the output blocking oscillator
composed of txa&MsU ' - end vj$, transformar T2, and associated components .
Tbe output blocking ovotUavW pro ndes composite frame syno pulses whloh ere de¬
livered to tbe Eight-Bit Shift Register and the Sync Selector at pin P. Resistor Rio
Is adjusted so that toe blocking oscillator fires reliably whenever n data pul— is
absent and do— not fire under any other oondltiona. A good setting of RIO would
be halfway between (1) the setting that Just begins to fire the output blocking o dilator
at clock rate, and (SJ the setting that stops firing the output blocking oscillator at date
pul— absence rate. This setting out be monitored at pins J and P .
7. 3. 3. 3 Eight-Bit Shift Register
The purpose of toe Fight-Bit Shift Register is to store data pul— absenoe or syno
pul— information for eight clock periods (of time) end pres— t to a succeeding AND
gate direct and stored sync pul— outputs.
This unit to composed of a series string o£ nine delay-ooupied flip-flops, four output
emitter followers, end a clock driver. The schematic diagram Is shown In Pig. A -40.
The first flip-flop mots as a buffer stage for toe succeeding eight units In toe shift
register. It stores the syno pul— a until the dock shifts this Information Into the
first storage flip-flop.
Three Inputs are provided: reset (dock) pul— a from the Frame Syno Separator
Revised 35 May I960
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nnnpor at nin S*
limn rail qa a from « a..»« ^ _ u * *. _i _ n _ i aL _
•j •“'■ r“*w'- “ *• w“* * * •**»« Mjiiv uopmiiiMi M|#|naii mi. pm r ; mjiu un
clock square wave from the Data Sync Separator appear* at pin M.
The reset pulse on pin S passes through diode CR1 and saturates transistor Ql.
When a sync pulse is present at pin P, current passes through diode CR2 causing
Q3 to saturate and the collector of transistor Ql to go to high potential. This allows
capacitor C5 to charge through RIO because diode CR7 is back-biased when transis¬
tor Q2 of the clock driver is cut off with a negative clock pulse. When transistor Q2
is saturated with a positive clock pulse, diodes CR7 and CR8 conduct because of the
previous charge on capacitor C6. This current flowing through diode CRB cuts off
transistor Q4 and saturates transistor Q5, thus setting up the first storage flip-flop.
In a like manner, the absence of a sync pulse will cause the first storage stage to be
set up in the opposite way with transistor Q5 cut off and transistor Q4 saturated.
This process continues through succeeding stages until the last stage is reached.
Two outputs are provided by the output emitter followers. Che output represents
stored sync pulses at pin U for delivery to the One-Bit Shift Register. The other out¬
put represents direct sync pulses at pin K for delivery to the One-Bit Shift Register.
7 , 3 . 3 . 4 One-Bit Shift Register
The purpose of the One-Bit Shift Register is to extract subcommutated sync pulses
from the Frame Sync Separator sync pulses and to combine them with sync pulses
from the Eight-Bit Shift Register. A schematic diagram of the One -Bit Shift
Register is shown In Fig. A-41.
This unit is composed of two delay-ooupled flip-flops. The first flip-flop acts as a
buffer stage and the second as a storage stage. Also included are two AND gates, an
OR gate, and a blocking oscillator.
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Five Input* are provided. Reset pulses from Ue Frame Sync Separator appear at
pin S. 8yno pulses from the Frame Sync Separator appear at pin P. Direct aync
pulses from the Sight-Bit Shift Register appear at pin K. Stored sync pulses from
the Eight-Bit Shift Register appear at pin X. The clock square wave from the Data
Sync Separator appears at pin M.
The single output consists of sync pulses for delivery to the main frame Sync Gate
and to the Sync Selector. These pulses appear at pin f.
The reset pulse on pin S passes through diode CR2 and causes transistor Q2 to
saturate. When a sync pulse is present at pin P, current passes through diode CR3
causing Q3 to saturate and the collector of transistor Q2 to go to a high potential .
This allows capacitor CR to charge through Rll because diode CR8 1b back-biased
when transistor Q1 is cut off with a negative clock pulse. When transistor Ql is
saturated with a positive clock pulse, diodes CR6 and CR9 conduct because of the pre¬
vious charge on capacitor C5. This current flowing through diode CR9 cuts off tran¬
sistor Q4 and saturates transistor Q5, thus setting up the storage flip-flop. In a like
manner, the absence of a sync pulse will cause the storage stage to be set up in the
opposite wr.j with transistor Q6 cut off and transistor Q4 saturated.
The output of the storage flip-flop now passes through an emitter follower composed
of translator Q6 and resistor R16 into an AMD gate composed of diodes CR12 and
CR13 and resistor R8. This output corresponds to the presence of a sync pulse on
pin P delayed for one bit of time.
An output from the buffer flip-flop Is taken from the collector of transistor Q2 and
corresponds to the presence of a sync pulse on pin P. It passes to the AND gate
through the emitter follower composed of transistor Q7 and resistor R17, where it is
ANDed with the Information from the storage Rip-flop. The output of the AND gate
(junction of CR12, CR13, and R8) is a positive pulse which corresponds to the
presence of two sync pulses on pin P one bit of time apart.
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This output now passes Into an OR gate composed of transistors Q8 and Q9, and
resistor R20. The second AND gate, composed of diodes CRH and CP. 15 and re¬
sistor R19, ANDa direct and stored sync pulses from the Eight-Bit Shift Register.
The output of the second AND gate, which corresponds to the presence of sync pulses
eight bits of time apart on pin P, also passes to the OR gate. The output of the OR
gate is coupled through capacitor C6 to the blocking oscillator composed of tran¬
sistors Q10 and Qll, transformer Tl, and associated components.
The output of the blocking oscillator is delivered to pin f as sync pulses to the main
frame Sync Gate and to the Sync Selector.
7 . 3 . 3 . 5 Sync Selector
The purpose of the Sync Selector is to combine sync pulses for recording purposes in
such a manner that only sync gate and keyed gate circuitry need be used to produoe
both main and subcommutated frame sync while in the reproduce mode . A schematic
diagram of the Sync Selector is shown in Fig. A -42.
In G-A, main frame sync pulses from the high-frequency sync gate appear on pin Z
and sync pulses from the One -Bit Shift Register appear on pin P.
Sync pulses enter at pin P and pass through an emitter follower composed of tran¬
sistor Q1 and resistors R2 and R4. These pulses than enter the gate circuit, which
is composed of transistors Q3, Q4, and Q5 and associated components, at the
emitter of Q4. Series switch Q4 and shunt switch Q5 are keyed by a pulee amplifier
composed of transistor Q3 and resistors R3 and R7 . This pulse amplifier ia operated
by subcommutated keying pulses, which appear on pin K in such a manner that the
presence of a keying pulse opens the gate and the absence of a keying pulse closes
the gate. Output pulses from the gate are passed through the emitter follower com¬
posed of transistor Q7 and resistor R12 for delivery to pin d as the subcommutated
sync pulse to sync gate. Output pulses from the gate are also passed through the
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follower composed of transistor v6 and resistor Ku end are ooupied through
capacitor C4 for delivery to the blocking oscillator, which is composed of transistors
Q8 and Q8 and transformer Tl.
Sync pulses also enter at pin Z and pass through emitter follower composed of tran¬
sistor Q2 and resistor R6 and are coupled through capacitor C3 for delivery to the
blocking oscillator.
T o blocking oscillator is fired by current pulses from either capacitor C3 or C4.
The poeitive output pulses of the blocking oscillator are delivered to pin f as
Comp site Frame Sync for the Record Electronics.
7. 3. 3. 6 Sync Cate
The purpose of the Sync Gate is to perml frame sync pulses to be generated only
when such pulses are anticipated. Sync pulses which are not true sync pulses are
sometimes produced by preceding sync separation circuits because of r-f interference.
Therefore, if a pulse can be supplied to arrive at a time when frame sync is expected
and this pulse keys a gate that follows the frame sync logic circuitry, then the chance
of producing false frame sync is greatly reduced. This card is made up of two one-
shots, two blocking oscillators, a flip-flop, a dual emitter follower, and a gate.
The schematic diagram for the Sync Gate is shown in Fig. A -43.
There are two inputs to the Sync Gate. Keying pulBes are delivered to pin a. Sync
pul sos from a shift register AND gate are delivered to pin Z. Frame sync output is
on pin f. The following is a description of a series of events which take place in the
Sync Gate circuitry.
The keying pulse from pin a resets the flip-flop composed of transistors Q3 and Q5
and associated components so that the output on the emitter follower composed of
transistor Q1 and resistor R2 (TP2) Pirns on the gate composed of transistor Q12
and resistors R36 and R37.
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Next, the anticipated sync pulse appears on pin 2. It is a positive pulse and it is
differentiated by capacitor Cl, diode CRl, and resistor &1 so that the positive -going
portion of the pulse triggers the ons-shot composed of transistors Q2 and Q4 and
associated components . This one-shot fires blocking oscillator no. 1, composed of
transistors Q6 and Q7, and transformer T1 at a time several microseconds after the
initial generation of the sync pulse In the Frame Sync Separator. The reason for this
delay Is that sync pulses generated in the Frame Sync Separator are approximately in
time phase with the data sync and that resetting of the pulse sequencers by the output
of the Sync Gat© (pin f ) must occur slightly after triggering by data aync. Thin delay
can be varied between 4 and 25 microseconds by adjusting resistor R3, but the delay
is usually on the order of 3 ( *1 ) microseconds.
" ‘ . U".
The positive-going output pulses of blocking oscillator no, 1 are delivered to the dual
emitter follower composed of transistors Q0 and Qll and associated components.
The output level of the dial emitter follower is seen at test point TP1, and is adjusted
by means of variable resistor B28 to 10 (+2.5) volts pesk-to-peak. '
The gate composed of transistor Q12 and resistors R36 and R37, which was opened
by the action of the flip-flop, passes a positive pulse that fires blocking oscillator
no. 2, composed of transistors Q13 and Q14 and transformer T2.
The output of blocking oscillator no. 2 is delivered to pin f as frame sync and to
one-shot no. 2, composed of transistors Q8 to Q10 and associated components.
One-shot no. 2 introduces a delay just long enough to Insure that the gate will pass
anticipated frame sync pulses. Variable resistor R34 should be adjusted so that the
flip-flop doses the gate approximately 3 microseconds after the generation of a
frame sync pulse at pin f .
Essentially the Sync Gate is a gate which is keyed "on” by the arrival of a pulse
wl ich Just precedes the anticipated sync pulse, it is keyed "off" if the anticipated
sync pulse passes through the Sync Gate. If no anticipated sync pulse arrives, the
Sync Gate remains open until an apparent sync pulse arrives.
Revised 25 May 1960
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TvS.S.7 Frequency Divider
jurjow of the Frequency Divider is to divide the repetition rate, or frequency,
of fkdaec by factors of two, four, or eight. Reset and set inputs are available for
each of the three cascaded flip-flops, or binary counters, so that outputs can be
phased la say desired manner.
When it is desired to operate pulse sequencers at rateB below that of clock, a fre¬
quency divider is inserted between the source of clock pulses and a low-speed pulse
sequencer. As the low-speed sequencers must sequence it certain times, reset
pulses nr?” st be properly applied to the flip-flops in use. In the O-A operation, the
frequency is divided by four.
All three flip-flop stages and associated output emitter followers in tho Frequency
Divider are similar. A schematic diagram is shown in Fig. A-44. Special attention
should be given the block diagrams because they can best describe the phasing of the
output in relation to the Frame Sync Reset pulse from the Sync Gate.
7 . 3. 3. 8 Eight-Channel Pulse Sequencer
The purpose of the Eight-Channel Pulse Sequencer is to provide eight channels of
pulses in time sequence. Seven flip-flops and eight AND gates are arranged to
accomplish this purpose. A schematic diagram is shown in Fig. A -45 .
Hie output pulses of the pulse sequencer are used to key data gates. The trigger
pulses determine the rate at which output pulses advance. The reset pulses deter¬
mine the phase of the output pulses In relation to the no. 1 output pulse.
Hie AND gates are driven by flip-flop outputs, which are isolated by individual
emitter follower stages.
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7. 3.3.9 Matrix
The purpose of the Matrix is to AND eight pairs of pulses from the Pulse Sequencers
to produce eight keying pulses for sample and hold circuits. A schematic diagram is
shown in Fig. A-46. The Matrix is composed of 16 emitter followers and eight diode-
type AND gates. Because all gates are identical, only the operation of the first AND
gate is described.
Positive pulses between the levels of approximately -IS and -5 volts appear on pins J
and Z and are coupled through emitter followers composed of transistor Ql, re
sistor R3, and transistor Q2 and resistor R5, respectively. Outputs of these emitter
followers pass to diodes CR1 and CR2. The coincidence of two positive pulses pro¬
duces a positive pulse at pin k as a keying pulse to the Sample and Hold circuitry.
7. 3. 3. 10 Data Gates
The purpose of the Data Gates is to provide eight data gates which are keyed by the
outputs of a series of AND gates. These AND gates are in turn keyed by pulses from
pulse sequencers. The Data Gate unit is made up of 12 emitter followers, eight AND
gates, and eight data gates. A schematic diagram of this unit is shown in Fig. A-47.
For any one of the AND gates to produce an output pulse, two ooincident input pulses
must be present. For example, to produce an output from AND gate 3, input pulses
must be present at pins J and V. Likewise, for an AND gate 2 output, input pulses
must be present at pins j and X.
All AND gates are composed of a single diode and a single resistor and possess two
inputs and one output. One input on each AND gate 1 through 4 are tied together and
receive input from pin j through the emitter follower composed of transistor Q2 and
resistor R3. In a like manner, one input on each AND gate S through 8 are tied to¬
gether and receive input from pin M through the emittt .• follower composed of tran¬
sistor Q7 and resistor R9. The other input on each AND gate 1 through 8 receive
Revised 25 May 1960
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Inputs from appropriate pins and emitter followers. Outputs of AND gates 1 and 8 are
ouuoied through emitter followers to pins d and K, respectively, as keying pulse
outputs. These outputs key individual data gates 1 through 8.
A data gates are identical. Each data gate la composed of an Inverting pulse ampli¬
fier, a shunt translator switch, and a aeries translator switch. Data gate 1 will serve
as an example of circuit operation.
AND gate 1 output pulse rises and falls between -IS and -5 volts. When the voltage is
greater than approximately -10 volts, transistor Q21 is turned on. The collector of
this translator, which serves as an Inverting pulse amplifier, drops to approximately
-10 volts. This voltage turns off transistor Q29 and turns on transistor Q13. Tran¬
sistor Q29 is the shunt switch and Q13 is the series switch. When the output from the
AND gate drops below approximately -10 volta, transistor Q13 turns off and turns
on Q29.
Whenever an output from an AND gate appears, the data gate will open and d-c video
from the Gate Driver Amplifier will appear. Whenever there is no AND gate output,
the data gate output will present a short circuit with respect to ground.
The gated outputs from data gates 1 through 8 are delivered to appropriate pins for
delivery to display electronics.
7.3.3.11 Pulse Set
The pu
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