Document text
Service Manual
H 52022-950J
Vol. 2
10 kHz — 1.01 GHz |
AM/FM SIGNAL GENERATOR
2022E
Part No. 52022-950J
) AMENDMENT RECORD
The following amendments are incorporated in this manual.
Amendment
No.
© Marconi Instruments Ltd. 1988
No part of this book may be reproduced or transmitted in any form
or by any means, electronic or mechanical, including photocopying,
or recorded by any information storage or retrieval system, without
permission in writing by Marconi ‘Instruments Lid.
Printed in the UK
Manual part no. 46881-891U
Print code : C-9/89
Oct. 88
are
CONTENTS
Page
Preface iii
Servicing precautions iv
Chapter 1 General information
Chapter 2 Installation See Operating Manual
Chapter 3 Operation ;
Chapter 4 TECHNICAL DESCRIPTION ‘4-1
Chapter 5 MAINTENANCE 5-1
Chapter 6 REPLACEABLE PARTS 6-1
Chapter 7 SERVICING DIAGRAMS 7-1
Chapter 8 MODIFICATIONS and SUPPLEMENTS
ASSOCIATED PUBLICATIONS 3
Part No.
Operating Manual, H 52022-950J Vol. 1 46881-890E
Operating Summary card 46881-892Y
46881-891U
Oct. 88
ER My,
PREFACE
WARNINGS, CAUTIONS AND NOTES
These terms have specific meanings in this manual:—
WARNINGS contain information to prevent personal injury.
CAUTIONS contain information to prevent damage to the equipment.
Notes contain important general information.
HAZARD SYMBOLS
The meaning of hazard symbols appearing on the equipment is as follows:-
. Symbol Nature of hazard Reference in manual
A Static sensitive device Page (v)
LN Component contains Beryllia Page (v)
MANUAL AMENDMENT STATUS
Each page bears the date of the original issue or the code number and date of the
latest amendment (Am. 1, Am. 2 etc.). New or amended material of technical impor-
tance introduced by the latest amendment is indicated by triangles positioned thus >.....<
to show the extent of the change. When a chapter is reissued the triangles do not appear.
Any changes subsequent to the latest amendment state of the manual are included on
inserted sheets coded C1, C2 etc.
SECURITY NOTICE
Second functions are grouped into three levels of operation. Access to the first two
groups, Normal and First level operation can be freely gained by carrying out the unlock-
ing procedures described in both Operating Manual and Service Manual. Details for
accessing the Second level operation however are only included in the Service Manual.
Some user units may wish to further restrict the distribution of this information to se-
lected calibration areas only. To enable this, Chapter 4 includes alternative pages
43a/44a which have the unlocking procedure deleted. Users may then withdraw either
pages 43/44 or 43a/44a as required.
46881-891U rm
Oct. 88 | ii
SERVICING PRECAUTIONS
“~ "This product has been designed and tested in accordance with IEC Publication 348 - ‘Safety
Requirements for Electronic Measuring Apparatus’. To keep it in a safe condition and avoid risk of
injury, the precautions detailed in the WARNINGS below should be observed. To avoid damage to the
equipment the precautions detailed in the CAUTIONS should also be observed.
WARNING - ELECTRICAL HAZARDS
AC supply voltage. This equipment conforms with IEC Safety Class 1, meaning that it is provided
with a protective earthing lead. To maintain this protection the mains supply lead must always be con-
nected to the source of supply via a socket with an earthing contact. Make sure that the earth protection
is not interrupted if the supply is connected through an extension lead or an autotransformer.
Before fitting a non-soldered plug to the mains lead cut off the tinned end of the wires, otherwise
cold flowing of the solder could cause intermittent contact.
Do not use the equipment if it is likely that its protection has been impaired as a result of damage.
Fuses. Note that there is a supply fuse in both the live and neutral wires of the supply lead. If only
one of these fuses should rupture, certain parts of the equipment could remain at supply potential.
Make sure that only fuses of the correct rating and type are used for replacement. Do not use
mended fuses or short-circuited fuse holders.
To provide protection against. breakdown of the supply lead, its connectors (and filter if fitted), an
external supply fuse with a continuous rating not exceeding 6 A should be used in the live conductor (e.g.
fitted in the supply plug).
Removal of covers. Disconnect the supply before removing the covers so as to avoid the risk of
exposing high voltage parts. If any internal adjustment or servicing has to be carried out with the supply
on, it must only be performed by a skilled person who is aware of the hazard involved.
Remember that capacitors inside the equipment, including any supply filter capacitors, may still be
charged after disconnection of the supply. Those connected to high voltage points should be discharged
before carrying out work inside the equipment.
WARNING - OTHER HAZARDS
Parts of this equipment are made from metal pressings, therefore it should be handled with due
care to avoid the risk of cuts or scratches.
Some of the components used in this equipment may include resins and other materials which give
off toxic fumes if incinerated. Take appropriate precautions, therefore, in the disposal of these items.
This equipment has a lithium battery which if incorrectly handled could cause a danger to health or
safety — refer to the Service Manual for safe handling precautions.
Beryllia (Beryllium Oxide) is used in the construction of the following components in this equip-
ment.
UNIT AB1/2: Transistor TR20
This material, when in form of fine dust or vapour and inhaled into the lungs, can cause a respira-
-tory disease. In its solid form, as used here, it can be handled quite safely although it is prudent to avoid
handling conditions which promote dust formation by surface abrasion.
Because of this hazard, you are advised to be very careful in removing and disposing of these
components. Do not put them in the general industrial or domestic waste or despatch them by post. They
must be separately and securely packed and clearly identified to show the nature of the hazard and then
disposed of in a safe manner by an authorized toxic waste contractor.
46881-891U
iv Oct. 88
gd
CAUTION - LCD HANDLING
When
operating or servicing this equipment take care not to depress the front or rear faces of the
display module as this may damage the liquid crystal display elements.
CAUTION - STATIC SENSITIVE COMPONENTS
Components identified with the symbol on the circuit diagrams and/or parts lists are static
sensitive devices. The presence of such devices is also indicated in the equipment by orange discs, flags
or labels bearing the same symbol. Certain handling precautions must be observed to prevent these
components being permanently damaged by static charges or fast surges.
(1)
(2)
(3)
(4)
46881-—891U
Oct. 88
If a printed board containing static sensitive components (as indicated by a warning disc or
flag) is removed, it must be temporarily stored in a conductive plastic bag.
If a static sensitive component is to be removed or replaced the following anti-static equip
ment must be used.
A work bench with an earthed conductive surface.
Metallic tools earthed either permanently or by repeated discharges.
A low-voltage earthed soldering iron.
An earthed wrist strap and a conductive earthed seat cover for the operator, whose outer
clothing must not be of man-made fibre.
As a general precaution, avoid touching the leads of a static sensitive component. When
handling a new one, leave it in its conducting mount until it is required for use.
If using a freezer aerosol in fault finding, take care not to spray programmable ICs as this
may affect their contents.
a
Chapter 4
TECHNICAL DESCRIPTION
CONTENTS
Para.
1 Introduction
2 Overall technical description
2 Frequency synthesizer and signal processing
4A Output
5 Modulation
11 Control
14 Synthesizer board (AA1/1)
14 250 — 500 MHz synthesis
36 BFO phase locking
38 Crystal oscillator (internal/external locking)
42 Angle modulation at low frequencies
45 Internal modulation tone
46 Microprocessor board (AA2/1)
A7 Microprocessor (IC2)
50 Address decoding
a2 Serial bus transceiver
53 Data transmission
57 Data reception
59 Memory
62 Timer
64 Memory protection
66 Synthesizer driver
68 RF processing board (AB1/2)
69 VCO system (250 - 500 MHz)
74 Frequency dividers (62.5 - 250 MHz)
82 Frequency doubler (500 -— 1010 MHz)
85 HF output stage (62.5 — 1010 MHz)
88 BFO system and LF output stage (10 kHz - 62.5 MHz) -
99 Power supply/control (A0/1 and A2/2)
100 Power supplies
110 Digital control section
121 Analogue control
128 Amplitude modulation above 62.5 MHz
134 Amplitude modulation below 62.5 MHz
137 Frequency modulation
145 Phase modulation
146 RF level control
150 RF filter tuning
152 Reverse power protection switching and attenuator drive
158 Jitter correction drive
46881-891U
Oct. 88
TECHNICAL DESCRIPTION
4
4
4
4
Para
160 Display and keyboard (A1/2)
162 Keyboard operation
165 LED display
166 LCD display
170 Two phase multiplexing
172 10 dB Step output attenuator (ACO and A2/2)
175 Reverse power protection (ACO and A2/2)
177. GPIB Adapter module (ADO)
181 Second function operations
Table Page
4-1 DAC values for various FM deviations (A2/2) ... 0) 34 =
4-2 Decoding of FM/®M functions (A2/2) «we 35 am 4
4-3 Attenuator switching logic (A2/2) Me, ede. + eee, ee ee 37
4-4 Attenuator logic (ACO and AQD): cc Ge ae Re 42
Fig.
4-1 Fractional N synthesis simplified block diagram ey ae 5
4-2 Four modulus prescaler circuit (AAI/1) -. et 6
4-3 Serial data transceiver (AA2/1) ne i, oes oe i
12
4-4 Data transmission (AA2/1)
12
4-5 Data reception (AA2/1) ... eee ee 13
4-6 Allocation of memory space (AA2/1) Ss Geb eek. oe ise
15 |
4-7 250 - 505 MHz VCO system simplified block diagram (AB1/2) es 18 :
4-8 Frequency dividers, simplified block diagram (AB1/2) ti. wa 20 =
4-9 Frequency multipliers, simplified block diagram (AB1/2) ... --- + 21... ae
4-10 HF output stage (62.5 - 1010 MHz) simplified block diagram (ABI /2) 22
4-11 BFO system & LF output stage (10 kHz — 62.5 MHz) simplified block
diagram (AB1/2) a ees Be. ue ea, eR te Se Oe 24
_12 Data conversion, simplified block diagram (A2/2) eee tee 28
_13 Serial data string (A2/2) 0.0 -- eee nee ee te ett 29
_14 Combining Aux., Ext. and Int. modulating signals (A2/2)... -. ++ 31
-15 AM signal path >62.5 MHz (A2/2) ... SGa'. <tek) es “eee ae 32
16 RF detector law (A2/2) .-. ee eee eee eee tt 33
-17 AM signal path <62.5 MHz (A2/2) ... ee 34
-18 Dual path FM drive (A2/2) -- wee ee 34
4-19 Phase modulation signal path (A2/2) ws, vee 36
4-20 Simplified RF level control signal path (A2/2) ... 0 eee 36
4-21 Typical waveforms, LCD drive waveforms (A1/2)) «.. eee eee ot 41
4-22 Internal structure of GPIB talker/listener integrated circuit, IC2 (ADO) 43
46881-891U
Oct. 88
4-2
‘ 2
he tal
“sega
TECHNICAL DESCRIPTION
INTRODUCTION
1. The following summary is an outline description of the instrument which may be
read in conjunction with two simplified block diagrams. The first is in the Operating
Manual and provides a simple guide to the main method of signal frequency generation.
Fig. 7-1 in this Service Manual is a more detailed diagram giving more specific
information.
OVERALL TECHNICAL DESCRIPTION
Frequency synthesizer and signal processing
2. 2022B is a synthesized AM, FM or phase modulated signal generator covering a
frequency range of 10 kHiz - 1010 MHz. Frequencies in the range 250 - 500 MHz are
generated from two voltage controlled oscillators. In the range 62.5 to 250 MHz signal
frequencies are obtained by divider circuits and in the range 10 kHz to 62.5 MHz by a
beat frequency oscillator (BFO) system. A frequency doubler is used to cover the band
500 — 1010 MHz.
3. The output frequency is phase locked to a frequency standard and frequencies up to
100 MHz can be set to a resolution of 10 Hz. Above 100 MHz the resolution is 100 Hz.
A fractional division scheme allows this resolution to be obtained whilst still keeping the
phase locked loop (PLL) bandwidth reasonably high. Provision is also made for the use
of an external frequency standard when this is preferred. Frequencies of 10, 5 or 1 MHz
can be used depending on the position of an internal link fitted within the instrument.
Output
4. Calibrated output levels from -127 dBm to +10 dBm are provided. A combination
- of ten output level calibration units can be selected on the front panel. The RF output
level can be set to a resolution of 0.1 dB over the entire output voltage range and features
a total cumulative accuracy of +2 dB. A precision attenuator provides 120 dB in 10 dB
steps and is a self contained module. Three 30 dB, one 20 dB and one 10 dB pad are
used whose frequency response is factory set. Each pad is operated by TOS relays.
20 dB of fine level control is achieved using PIN diode attenuators.
Modulation
5. Amplitude, frequency and phase modulation can be provided internally from a
free running switchable modulation source.
6. Amplitude modulation. For carrier frequencies greater than 62.5 MHz, modulation
is obtained using PIN diode attenuators and envelope feedback. At carrier frequencies
less than 62.5 MHz modulation is provided by a fixed frequency modulator operating at a
frequency of 160 MHz. AM is DC coupled when the modulation ALC is off.
7. Frequency modulation. FM is created by applying the modulation signal to.
varactor(s) in the 250 - 500 MHz oscillator. _ Simultaneous modulation of the reference
frequency prevents fall off in response below the loop bandwidth. FM off (CW mode)
gives the lowest residual FM noise. The low frequency response is tailored to optimize
the modulation accuracy of low frequency square waves.
8. Phase modulation. This is achieved using a differentiator in the modulation signal
path and then applying the differentiated signal in the same manner as the FM.
46881-891U
Oct. 88 4-3
(ASR ec ASC ee a etcetera ad +, ana aca rR eS amare mney SSS
TECHNICAL DESCRIPTION
9. Modulation signal ALC. This is always in circuit when internal modulation is in
use and may be selected when switched to external modulation. The circuit uses a JFET
and automatically levels signals in the 0.9 to 1.1 V range to maintain accurate
modulation. Outside of this voltage range HI or LO messages appear in the modulation
display area to warn the operator of an error. |
10. Auxiliary modulation. A rear panel socket allows an external modulation signal to
be combined with the internal modulation signal. A signal level of 1 V RMS at this socket
will produce 20% of the indicated modulation setting.
Control
11. Front panel operation is carried out by direct entry of required settings via the
keyboard. | Microprocessor control ensures flexibility, simplicity of use and allows
programming by the General Purpose Interface Bus (GPIB). This facility is offered as an
optional accessory enabling the instrument to be used both as a manually operated bench }
mounted instrument or as part of a fully automated test system. C
12. Both analogue and digital circuits are incorporated to control the instrument. Three
methods of data transfer from the microprocessor to the remainder of the instrument are
used:—
(1) The VCO frequency is set by direct parallel loading from the microprocessor
to the synthesizer board.
(2) Analogue control of functions such as a.m. depth and RF level is maintained
by first converting data into a serial format then transmitting it from the micro-
processor/synthesizer box. The data is then converted back to an 8-bit parallel
format which is loaded into Digital-to-Analogue Converters (DACs). This causes
gain changes which vary voltage levels as appropriate.
(3) The third method is to convert the parallel data on the control board into a
special serial format that is fed to the liquid crystal display drivers.
13. The microprocessor used is an 8085A and incorporates an 8-bit multiplexed datal
low order address structure to allow a 16-bit address bus. 2 K bytes of RAM are used
for temporary storage. 32 K bytes of EPROM are used for the instrument’s operating
program and 2 K bytes of non-volatile EAROM are available for user control settings and
calibration information.
46881-891U
4-4 Oct. 88
TECHNICAL DESCRIPTION
SYNTHESIZER (AA1/1)
Circuit diagram : Fig. 7-6
250-500 MHz synthesis
14. This is accomplished by fractional N synthesis and is made up of a system divided
into three areas as follows:—
(1) 40 kHz synthesizer. A conventional type operating in 40 kHz increments and
consisting of a fully programmable divider, a 40 kHz reference divider, a phase/
frequency comparator and a loop filter.
(2) Fractional N accumulator. Whose purpose is to make periodic modifications
to the division ratio of the synthesizer so that the average division ratio is a frac-
tional value (i.e. interpolating between the 40 kHz increments).
(3) A jitter correction circuit. Whose function is to correct for the unequal spacing
of the divider output pulses caused by the operation of the accumulator.
Fret
PROGRAM-
MABLE
DIVIDER
N,N +1 JITTER
CORRECTION
Fig. 4-1 Fractional N synthesis simplified block diagram
15. Fractional N synthesis. In single-loop synthesis the minimum frequency incre-
ment attainable is equal to the reference frequency. Thus fine frequency increments can
only be attained at the expense of a very low reference frequency. This requires
extensive filtering at the loop filter, resulting in a low loop bandwidth and consequent
poor performance. Fractional N synthesis overcomes this restriction.
16. Increments smaller than the reference frequency are generated by making periodic
adjustments to the division ratio so that the average value of division is actually a
fractional number. The output pulses from the programmable divider no longer have a
uniform spacing and this must be corrected before the signal reaches the phase
comparator otherwise spurious modulation or ‘jitter’ will occur. The circuit that com-
putes the adjustments to the division ratio also generates a correction voltage and this is
used to delay the output pulses to return them to uniform spacing, eliminating the jitter.
46881-891U
Oct. 88 4-5
LEE 22, OTR EY EMS i SE a oN Tete ten ote can mamemeee teapars eS eS
TECHNICAL DESCRIPTION
17. 40 kHz synthesizer. The 10 MHz internal crystal oscillator X1 is divided down to
40 kHz by the action of IC2a, IC8a,b, IC14a, IC20b,c and fed to IC22 phase/frequency
comparator. A 250 - 505 MHz input from AB1/2 RF processing board drives IC9 four
modulus pre-scaler via PLX and C4. Internally this consists of two cascaded two-
modulus 15/16 pre-scalers. Both normally divide by 16 giving a total modulus of 256. If
IC9 pin 4 (control A) is taken to logic ‘low’, then in the following output cycle the first of
the 15/16 dividers is set to 15 for just one count cycle. Thus the modulus is reduced to
255:
18. If IC9 pin 5 (control B) is taken ‘low’, then the second 15/16 divider is set to 15,
however as this is preceded by the other divider (which is dividing by 16) then the
modulus falls to 240. If both control pins 4 and 5, are taken low, the modulus falls to
239.
19. IC9 pre-scaler is used in conjunction with four programmable counters 1C4,ICS,
IC16 and IC17. The nominal modulus of the pre-scaler is 256 and so the data loaded |
into IC16/IC17, counter C, determines the number of times that 256 is counted. IC4 and 4
- JCS, counters A and B, modify the division ratio of the pre-scaler for some of the time.
} 6-BIT
| COUNTER |
. Cc’
IC1G/IC17
4-BIT |
COUNTER |
‘B’
Ics
4-BIT |
COUNTER |
a A’ |
Fig. 4-2 Four modulus prescaler circuit (AAI/I)
20. Counter B is loaded with data that reduces the division ratio of the pre-scaler by 16
for anything up to sixteen output cycles of the pre-scaler. Counter A is loaded with data
that reduces the division ratio of the pre-scaler by 1 for up to sixteen output cycles of the
pre-scaler. Total division ratio is (256 x C) - (16 x B) - Aso providing a division ratio
that is fully programmable.
21. Operation. The data is loaded into the counters and if this is not zero the terminal
count (TC) outputs of both A and B counters will be low and a modulus change is
activated. IC9 pre-scaler output then clocks the counters IC4,IC5 (which are hard-wired
to count down) and within sixteen counts ‘A’ and ‘B’ will reach zero, the two control lines
will be returned to logic ‘high’ state and further counting is inhibited.
46881-891U
4-6 Oct. 88
TECHNICAL DESCRIPTION
22. Counter ‘C’ continues to count until it too reaches zero and TC is taken to logic
‘high’. This sets IC11b latch which in turn produces an output pulse to activate the
LOAD inputs of all three counters. When the CLOCK line is next asserted to logic ‘low’
IC11b latch is released and the counters are ready to count on the next positive-going
clock transition. IC16 and IC17 together form counter ‘C’ and IC11b combines both TC
outputs to implement the latching function. IC17 TC goes ‘high’ first setting the D input,
then IC16 TC follows, clocking the terminal count onto the output.
23. A fractional N synthesizer requires an additional control line to cause the total
division ratio to be changed by one. This line originates from IC27 pin 14. If this line is
logic ‘high’ ICi1a pin 1 will also be held ‘high’. IC4 counter ‘A’ TC line is routed via
IC10a and gated with the Q output of IC11a to the pre-scaler Control ‘A’ (CTA) line.
This allows the option of holding the CTA line logic ‘low’ for an extra count and changing
the division ratio by unity. Towards the end of a division cycle IC4 pin 12 will also be
‘high’ and IC11a pin 6 will be clocked ‘low’. This activates the preset input and locks
re IC11a, pin 6, ‘low’. IC10a pin 2 is therefore held ‘high’ and TC is effectively connected
eat directly to IC9 CTA and the division ratio is unmodified.
24. If the line from IC27 pin 14 is low and IC11b produces a divider output pulse, this
appears as a negative-going pulse on IC11a pin 1 and clears IC11a during the time that
the counters are being loaded. IC10a pin 2 is now held ‘low’ and cannot return ‘high’
until IC4 pin 12 goes ‘high’ and the subsequent pre-scaler clock pulse is received. Thus
the line to pre-scaler CTA is held low for one extra count and the division ratio is
reduced by one.
25. Phase/frequency comparator. This comprises IC22 and IC20d. The output of the
programmable divider is routed to IC22 pin 11 via a jitter correction circuit, (described
later). If the leading edge of the pulse arrives before the reference divider pulse at IC22
pin 3 then the VCO frequency is too high. IC22 pin 8 is then set ‘high’ and returns ‘low’
after the reference divider pulse is received on pin 3. TR8 conducts drawing current into
the loop filter circuit IC28, causing the voltage at IC28 pin 6 to decrease. If the pulse
from the programmable divider arrives after the reference divider pulse then pin 5 is set
‘low’ and TR7 conducts and raises the voltage at IC28 pin 6. R27 and C23 delay the
ae resetting of the circuit by approximately 50 ns to maintain at equilibrium a finite pulse
a width to both TR7 and TR8. In this way phase response is improved (dead spots are
avoided).
26. R35, C27 and C28 form part of the loop filter in conjunction with other com-
ponents on AB1/2. Dividing the loop filter components in this way reduces the sensitivity
to unwanted external pick-up and allows interconnections to be made between AA1/1 and
AB1/2 using ribbon cable. There are two output lines, VCO TUNE A is the output to
AB1/2 via PLT pin 14, VCO TUNE B (PLT pin 13) is a dedicated earth return from AB1/2
to prevent the formation of a hum loop through the instrument chassis.
27. Fractional N accumulator. This system has an improved resolution of 4000 over
the 40 kHz synthesizer previously described and gives 10 Hz increments. This iS
accomplished by making periodic modifications to the division ratio such that the average
division ratio is the required fractional value. So in a sequence of 4000 output pulses
from the programmable divider, the division ratio could be modified for 0 — 3999 of these
periods. If the division ratio is modified from N to N+1 for M of the 4000 periods, then
the average division ratio becomes N+M/4000 and the average output frequency becomes
Nest nea—“© x 40 kHz.
4000
46881-891U
Oct. 88 4-7
Tat
TECHNICAL DESCRIPTION
28. The purpose of the accumulator is to generate the sequence of division ratio
modifications. The accumulator has a capacity of 4000 and is clocked from the output of
the programmable divider. At each clock pulse the vaiue M is added to the contents of
the accumulator. When the accumulator overflows, a division ratio change is imple-
mented in the next period. At the end of 4000 periods, the total number loaded into the
accumulator will be 4000 x M and thus M overflows will have been created during this
time. The overflow occurs with approximately uniform spacing considering that M may
not be on an exact sub-multiple of 4000.
29. The output pulses from the programmable divider no longer have a uniform
spacing because periodic changes have been made to the division ratio. If these changes
are allowed to reach the phase comparator, error signals would result and modulate the
VCO causing unwanted frequency jitter. This is prevented by the incorporation of a jitter
correction circuit which is described below.
30. Jitter correction circuit. When M is unity or close to it this could correspond to a
10 Hz offset from a 40 kHz frequency multiplier. The programmable divider will be
dividing by N for 3999 times and then N + 1 just once. This is seen by the phase
comparator as a gradually increasing phase error that is occasionally pulled back to zero.
This occurs because the correct division ratio is N+1/4000 and the N error is slight, the
N1 error however is much greater so that while the divider is dividing by N each suc-
cessive pulse is arriving a fractional amount sooner with respect to the reference. When
the N+1 division is implemented the pulses are brought back into line.
31. To return the pulses to a uniform spacing and prevent jitter involves the retarding of
the programmable divider during the time it is dividing by N, then removing the retarding
when the N+1 period is reached. The count resident in the accumulator is proportional to
the amount of retarding needed and represents the phase error referred to the input of the
programmable divider. As the accumulator fills, the phase shift is increasing and the
overflow occurs when one cycle of phase shift has accrued. The implementation of an
N+1 division at this point effectively swallows that extra cycle, returning the phase shift to
zero.
32. Jitter correction is implemented by feeding the contents of the accumulator into a
digital-to-analogue converter. An output voltage proportional to the retarding is pro-
duced and is used to set the threshold on a comparator. A second input is fed from a
ramp triggered from the output of the programmable divider. The coefficient of the
resultant voltage-to-time conversion is set so that the full swing of the digital-
to-analogue converter produces a change equal to one cycle at the input of the
programmable divider. This is in the range 250 - 500 MHz resulting in timing changes
from 4 to 2 ns from which the required coefficient is inversely proportional to the
synthesizer frequency and is accommodated by varying the reference voltage to the
digital-to—analogue converter.
33. Operation. IC25-IC27 form a 12-bit full adder. The value M referred to in pre-
vious paragraphs is latched into 1C23 and 1C24. 1C31 and IC32 form a 12-bit edge-
triggered data latch. 1C29 and IC30 can be assumed to be transparet t in this instance.
Feedback from IC31 and IC32 to the input adders 1C25-IC27 form an accumulator. Each
time the latches are clocked (IC31,32 pin 9) the new output is summed with M and the
result presented back to the input of the latches. Overflow, when it occurs, appears at
1C27 pin 14.
46881-891U
4-8 Oct. 88
shh
SPE,
Bicone
TECHNICAL DESCRIPTION
34. The accumulator is required to overflow at 4000 and not 4096 which would nor-
mally be the case. This is achieved by IC29 and IC30. An overflow causes IC29 pins 3 ....
and 5 to go to logic ‘high’ and this adds 96 to the number fed back to the latch. The size
of the accumulator is thus effectively reduced to 4000 although all the output numbers are
96 higher than normal. This is of no consequence as only the relative phase of the
correction signal is important. The overflow line (IC27 pin 14) is fed back to the pro-
grammable divider where it implements the division ratio change previously described.
1C33 is a multiplying digital-to-analogue converter, the frequency dependent reference
voltage arriving on pin 15 via PLT pin 1. This reference is generated on A2/2 board.
35. The jitter correction circuit comprises C50 normally shunted by TR9. When the
programmable divider outputs a pulse TR9 base is taken low and C50 charges via R39
and LA. A ramp is generated with a duration which is sufficiently brief that the current
in LA remains reasonably constant and the ramp linear. When the voltage exceeds the
voltage from the digital-to—analogue converter by 0.6 V, TR10 conducts and an output
pulse is produced to trigger the phase comparator. The greater the voltage from the
digital-to-analogue converter, the longer the time delay.
BFO phase locking
36. The 160 MHz oscillator on AB1/2 board is locked to the 10 MHz frequency
standard. The circuit comprises a fixed ratio divider (modulus 16), a phase/frequency
comparator and a loop filter. The 160 MHz signal is fed to IC1 pin 1, via PLU pin 1.
IC1 pin 8 is biased to prevent self-oscillation of IC1 in the absence of a signal. Output is
fed to IC6 pin 3 and a 10 MHz reference to pin 11.
37. The circuit functions in a similar manner to IC22 but because the frequency is
higher, Shottky TTL is used and the feedback delay components are omitted. IC6
outputs on pins 5 and 8 turn on TRI and TR2 respectively. C10,C12 and Li form a
low-pass filter to prevent the feedback of 10 MHz components to AB1/2. The loop filter
itself is on AB1/2 board.
Crystal oscillator (internal/external locking)
38. External standard operation is accomplished by phase-locking of the internal 10
MHz crystal oscillator rather than by its substitution with the external signal. The
method effectively eliminates spurious signals that may be present on the external
standard. A further advantage is that if gross frequency errors occur in the external
standard or if it fails completely, this would be flagged as an error condition but the
instrument will continue to function on the internal oscillator. The internal oscillator is
based on a Colpitts circuit, the frequency stability being governed by the characteristics of
the quartz crystal.
39. External standard is fed via PLS pin 1 to the Schmitt trigger IC34 pins 1 and 2, R5
assisting in terminating possible reflections. When EXT STD is selected, IC2 pin 2 is set
‘high’ allowing the signal to reach IC7 pin 11. The crystal oscillator output is divided to
5 and 1 MHz by IC8a and either 10,5 or 1 MHz (dependent on the link setting) is routed
to IC7 pin 3 which, like IC6 and IC22, is used as a phase-frequency comparator. Links
can be reset as described in Chapter 5 Maintenance. TR3 and TR4 outputs are summed
across C15 which together with R1 and the rear panel frequency adjustment form the loop
filter. When INT STD is selected no clock pulses arrive at IC7 pin 11. In this condition
pins 5 and 8 are static and both TR3 and TR4 are turned off. The voltage on crystal
oscillator X1 pin 5 is now determined solely by the setting of the rear panel adjustment.
46881-891U
Oct. 88 4-9
TECHNICAL DESCRIPTION
When selected to EXT STD, pulses are coupled to the emitter of TR3 or TR4 depending
on the direction of phase error and their output voltage fed to the crystal oscillator to
achieve phase lock.
40. Two detection circuits are incorporated to prevent incorrect operation. D5,D6, C13
and C14 form a signal detection circuit. IC15 pin 1 only goes to logic ‘high’. when a
signal is present at IC34 pin 3. IC12b and IC12c together with D8 and D9 form a
window comparator. If operation with an external standard causes the crystal oscillator
tuning voltage to fall below 1 V, or rise above 10 V, IC15 pin 2 will be set to logic ‘low’.
41. When EXT STD is selected, IC2 pin 2 is taken ‘high’. The sense of the EXT STD
VALID line is tested (IC15 pin 3) and if this is logic ‘ow’ operation is correct. [If it is
‘high’ this would indicate that the external standard has either an incorrect level, incorrect
frequency or is non-existent. In this condition the processor takes IC2 pin 2 to logic
‘ow’ and returns the instrument to INT STD. The sense of IC15 pin 3 is again tested. If
this is still ‘high’ then the signal is not being detected and therefore is either non-
existent or at too low a level. If however the sense of IC15 pin 3 is logic ‘low’ then it is
the signal frequency that is incorrect. The appropriate error message is displayed and
the testing sequence continued until either correct operation is detected or the instrument
is returned to INT STD by the user.
Angle modulation at low frequencies
42. The 250-500 MHz synthesizer has a loop bandwidth of approximately 200 Hz
giving the best compromise between switching speed and reference breakthrough. Inside
this bandwidth, FM applied solely to the VCO will be attenuated due to the loop error
correcting action. Since it is necessary to replicate a 10 Hz square wave, the response
must be extended below that of the VCO phase locked loop. To achieve this the FM is
effectively applied to the reference side of the loop in the same sense as that applied to
the VCO and with the same deviation expressed as a percentage of its frequency. This
means that no error signal is produced at the output of the phase frequency comparator
and the FM is successfully implemented.
43. When FM or ©M is selected the 40 kHz reference is routed via a phase modulator .-
comprising TR5,TR6 and IC18. IC14 pin 7 produces a positive-going pulse and this
turns on TR6 discharging C17. TR6 then turns off and C17 is charged via TR5 which is a
current source. When the voltage on IC18 pin 2 exceeds that on pin 3, pin 7 goes to logic
‘high’ and in turn clocks the reference input of IC22, phase frequency comparator. The
time delay thus produced is in proportion to the voltage applied to IC18 pin 3.
44. The FM signal is processed on A2/2 board and this is scaled and integrated so as to
represent the degree of phase modulation required. It is then applied to 1C18, pin 3 via
PLT pin 10. In CW operation, IC20 pin 2 is taken to logic ‘low’ and pin 13 logic ‘high’.
The 40 kHz reference is now routed from IC14 pin 6 through to the phase comparator and
the modulator is bypassed. This ensures the best possible noise performance in the CW
mode.
Internal modulation tone
45. The internal oscillator is based around a Wein bridge circuit with a FET levelling
loop. IC36a is the main oscillator, the timing component being switched by IC35.
Levelling is performed by adjusting the gain around IC36a by means of TR13 via an error
signal supplied by IC36c derived from a positive peak detector D1 6,C76. The output
46881-891U
4-10 Oct. 88
TECHNICAL DESCRIPTION
level is set by R81 while IC36d provides buffering of the 1 V RMS audio signal.
Additional output filtering is provided by a filter network in RF box A AA0O/2 to remove
any high frequency synthesizer noise.
MICROPROCESSOR (AA2/1)
Circuit diagram : Fig. 7-7
46. The microprocessor controls the flow of data necessary to drive both address and
data bus lines. Information from the keyboard or the GPIB is received to control such
functions as RF level, Modulation depth and Carrier frequency. Transmission of data to
the appropriate latches may either be direct onto AA1/1, or via a serial link to A2/2.
Functions of the board are divided into the following areas:—
(1) Microprocessor (5) Timer
(2) Address decoding (6) Memory protection
(3) Serial bus transceiver (7) Synthesizer driver
(4) RAM, PROM and EAROM memory
Microprocessor (IC2)
47. The 8085 Microprocessor IC2 has an 8-bit multiplexed data/low order address
structure to allow a 16-bit address bus. The 8 least significant bits of the address bus.
are demultiplexed by the latch ICS. IC2 is clocked on pin 1 by a 5 MHz signal and is
divided internally to provide two non-overlapping 2.5 MHz phases.
48. Three restart lines (or interrupts) are available. RST 7.5 is positive edge triggered
and handles most of the instrument interrupts such as GPIB, keyboard, RPP and
modulation HI/LO signals. These are described in A2/2 board technical description.
RST 6.5 and RST 5.5 are level controlled (logic ‘high’ causing a jump). RST 6.5 is fed
from AA1/1 synthesizer board and will go ‘high’ if the external frequency standard when
selected, is not valid. RST 5.5 is used for the timing process monitoring the instrument’s
elapsed time.
49. A number of test points available on the board (TP3-TP12) are only used when
factory testing the board initially. Two lines that are normally used for serial data
transmission are available, SID and SOD on pins 4 and 5. In this application SID
monitors the state of the EAROM, IC13, whilst SOD allows the timer to operate correctly.
- The RESET L (pin 36) is an input which if taken ‘low’ will cause the processor to jump to
the initializing routine when the RESET line on pin 3 is taken ‘high’ again. This facility
is used to prevent spurious addressing of any memory locations during power failures.
Address decoding
50. The 8 least significant bits (AO - A7) of the address are de-multiplexed from the
data/low order address bus. This is carried out by IC3. When the address enable line
(ALE) is taken ‘high’ data present on IC3 pins 3,4,7,8, 13,14,17 and 18 are latched onto
the corresponding outputs of IC3.. The data bus can then be used to read or write
information to the appropriate location dependent on the state of the RD L and WR L
lines on IC2 pins 31 and 32. The appropriate location could be any memory IC or one of
a number of latches used to interface between boards.
46881-891U
Oct. 88 4-11
TECHNICAL DESCRIPTION
51. IC8 provides further address decoding for the three most significant address bits.
RESET line, pin 4 ensures that the outputs of IC8 are disabled if the +5 V rail falls below
+4.5 V. All outputs will be set ‘high’ if TP2 goes ‘low’ or pin 4 goes ‘high’.
Serial bus transceiver
RITE LO SET TO
WRITE LOW READ
STROBE CLOCK DATA|
|
i TRANSMIT /RECEIVE
{ OUTPUTS GO
LO WHEN
SELECTED )
Fig. 4-3 Serial data transceiver (AA2/I)
52. This arrangement is used to communicate with all devices mounted outside the RF
box AAO. Plug PLAC carries three lines to effect data transfer, see Fig. 4-3. These are
pin 4, CLOCK, pin 5, STROBE and pin 6, DATA. The DATA line is bi-directional
whilst the CLOCK and STROBE lines only carry information out from the microprocessor
board. The +5 V supply rail and the RST 7.5 INTERRUPT line together with an earth are
the remaining connections made via PLAC.
Data transmission
53. To obtain the required sequence, information is set up one bit at a time on the data
line, then the CLOCK line is asserted ‘high’. The positive edge of the CLOCK pulse will
enable the shift registers on A2/2 board to accept the data. The STROBE line will be
taken ‘high’ to transfer data entered in this manner to the registers when. appropriate.
Fig. 4-4 shows the basic circuit arrangement for data transmission.
54. IC8 is configured to appear as a part of the memory space and is written to when
data is to be clocked into IC11. Taking IC8, pin 10 ‘low’ allows the WR L from the
microprocessor to pass through IC8c to the clock line of IC11. IC8a routes those WR L
signals for which address lines ADO and AD1 are decoded to define one of four paths.
For serial data transmission AD1 is ‘low’ and ADO is ‘high’.
46881-891U
4-12 Oct. 88
“ff 2 3
er
TECHNICAL DESCRIPTION
CLOCK
Fig. 4-4 Data transmission (AA2/1)
55. After a data bit has been written onto the DATA line (PLAC, pin 6) a clock edge is
generated by writing a different word to IC11. This byte consists of 02H for the clock
information and 01H or 00H for the data information, the latter determines what goes
into the latches on A2/2.
56. STROBE. If data just sent is to be latched onto the outputs of A2/2,IC5,IC7 and
IC9, a byte equal to 01H will be written to IC8’s address. This will cause IC11, pin 5 to
be taken ‘high’ and that level will be clocked through. This will take the STROBE line of
all latches ‘high’ allowing the data present at that time to be transferred to their outputs.
Data reception
AD
3
DATA CLOCK
Fig. 4-5 Data reception (AA2/I)
57. In order to send information from A2/2 to AA2/1, microprocessor, data is clocked
out from an eight bit shift register into a memory location in the processor’s memory
space. By rotating the bit addressed in the latter the serial to parallel conversion can take
place. To realize this the arrangement on AA2/1 is slightly altered. Fig. 4-5 shows how
this occurs. IC11, pin 2 is taken ‘high’ which disables IC10c. IC10b pin 13 is taken ‘low’
when appropriate to allow the data from A2/2 to have control over the data/address line
ADO.
58. IC11 pin 10 is the CLOCK output whose positive edge will be used to cause a
further data bit to come from A2/2, IC8, Q8. This is achieved by sending a ‘high’ level
to IC8 pin 10 via IC5,IC6a and IC26c. The data bit, entering at PLAC pin 6, is read into
a RAM location from where it may be addressed for further use.
46881-891U
Oct. 88 4-13
TECHNICAL DESCRIPTION
Memory
59. RAM. IC12 is a2 K byte (1 K = 1024) static CMOS RAM chip which is used as a
temporary store for the intermediate stages in calculations such as Level conversion from
dBm to pV.
60. EPROM. IC7 is a 64 K byte store for the instrument’s operating programme. Each
integrated circuit is an ultra-violet erasable programable read only memory which is
programmed during initial manufacture and should be considered as a read only memory.
61. EAROM. IC13 provides 2 K bytes of non-volatile memory and stores data which
includes calibration information and control settings entered by the user. To avoid
accidental corruption of the stored data two protection schemes are incorporated, one of
these is written into the instrument’s software and is described in the second function
details. The other is a hardware circuit, “memory protection” which is described in later
paragraphs. IC13 pin 1 READY/BUSY line is used to inform the microprocessor when a
write command has been executed.
46881-891U
4-14 Oct. 88
=f
TECHNICAL DESCRIPTION
FFFF
E000
DFFF
SERIAL BUS CODING AND SYNTHESIZER
LATCH ADDRESSING
Co00 Serial Out C0002 Synth Data
C000 C001 Serial Out C003 Synth Latch address
BFFF
A7FF
A000
QFFF
87FF
8000 IC12 RAM
7FFF
IC7 EPROM
0000
Fig. 4-6 Allocation of memory space (AA2/1)
Timer
62. Allowance is made in this circuit for the user to monitor the instrument’s total
number of running hours to date. This timing facility. is particularly useful when
recalibration periods are to be determined after a given number of hours. IC3, IC4 are
used as dividers to allow sensibly long timing intervals to be achieved. . IC3 is configured
as an eight bit counter which then feeds IC4 a fourteen bit counter. This in turn causes a
level triggered interrupt (RST 5.5) when its output is set ‘high’.
46881-—891U
Oct. 88 4-15
TECHNICAL DESCRIPTION
63. IC3 and IC4 count to ~2.1 x 106 and the RST 5.5 INTERRUPT occurs every ~840
ms. Each interrupt clocks a further software counter until after a 15 minute period a new
entry is made to data in the non-volatile memory of IC13. Two elapsed time readouts
correct to within 30 minutes can be observed on the front panel display via second
functions 9 and 198.
Memory protection
64. To ensure that the integrity of data in the non-volatile memory is maintained it is
essential that there is no risk of writing to it whilst the microprocessor is not completely
functional. This can occur if the +5 V rail falls to some undefined level. In this event
IC1 and its associated circuit will come into operation.
65. IC1 compares the +5 V rail with a stabilised voltage derived from the +24 V rail. If
the +5 V rail falls below 4.5 V the RESET LINE of the microprocessor (IC2) will be held
low due to TR2 being turned on. This inhibits operation of the microprocessor until the
+5 V rail rises above +4.5 V at which time the 2022E will re-initialize itself. This circuit
is in addition to the internal protection against low supply volts that is present in the
EAROM IC13.
’ Synthesizer driver
66. AA1/1, Synthesizer board requires 26 bits of data to set the oscillator frequency (226
x 10 Hz ~671 MHz which is the nearest factor to 500 MHz) and 4 bits of control data.
AA2/1, IC14 and IC15 allow this data to be transferred from the microprocessor to the
synthesizer. 1C14 acts as an address latch whilst IC15 controls six data lines on PLAB,
pins 5-10.
67. Both of these latches are configured as part of the memory address space, see Fig.
4-6, and are merely written to when frequency data is to be updated. IC8 provides the
~ address decoding and controls the routeing of the WR L path through IC9b and d. A
positive edge transition on IC14 or IC15, pin 9 will transfer input data to the outputs.
46881-891U
4-16 Oct. 88
‘y
TECHNICAL DESCRIPTION
RF PROCESSING BOARD (AB1/2)
Circuit diagram : Fig. 7-8
68. This board houses the entire RF generation system and is comprised of five signal
generation circuits briefly described as follows:-
(1) 250 - 505 MHz - A conventional VCO system employing two oscillators, each
one operates over a half octave with a changeover point at 353 MHz. A tunable
notch filter reduces second harmonic content of the output. :
(2) 62.5 - 250 MHz - This frequency range is obtained by dividing down the VCO
frequency range with the divide-by-two networks. Low-pass filters are employed
to reduce the harmonic content.
(3) 500 - 1010 MHz - The VCO output is fed to a frequency doubler circuit which
comprises a balanced transformer and diode bridge. Insertion loss is compen-
sated for by an additional amplifying stage. A voltage tuned band-pass filter
enables sub-harmonic and harmonic components to be reduced.
(4) 62.5 - 1010 MHz output stage. This stage provides an automatic levelled
output over the range +10 dBm to -7 dBm and also the means of DC coupled ampli-
tude modulation. The output is converted to a 50 Q source and fed to a relay
selecting either this output or that of the BFO system. The output is fed to an cutput
amplifier which is protected from reverse power by a pair of diodes.
(5) 10 kHz - 62.5 MHz BFO system. A phase locked 160 MHz VCO signal is
used as one input to an RF mixer. Amplitude modulation is superimposed on this
signal before mixing with a signal in the range 160.01 to 222.5 MHz derived from
the output of the first divide-by-two network. The IF output of the mixer 0.01 -
62.5 MHz is then filtered to remove unwanted mixer products. A final amplifier
_ stage provides a voltage gain of 33 dB and acts as a 50 Q source. The output level
is also peak detected and fed back to an input error amplifier to provide automatic
level control and allow DC coupling of the amplitude modulator. The output is fed
to an output amplifier which is protected from reverse power by a pair of diodes.
46881-891U Me wn
Oct. 88 N, 4-17
3R
TECHNICAL DESCRIPTION
VCO system (250-505 MHz)
353-505MHz | | BUFFER
VCO TUNE R21 | i
PLAD (16) oe VCO | if SOSMHz
(HIGH) | | | LPF
hot
FM INPUT ics | CONTROL
PLAD (12) « = in:))
BUFFER
OSC HIGH
PLAD (10)
BUFFER ¢
TO DIVIDER
| CIRCUITS
I ictta, b
Fig. 4-7 250-500 MHz VCO system simplified block diagram (ABI/2)
69. Two oscillators are used to cover the basic frequency range each one generating one
half octave. Changeover occurs at 353 MHz. The upper half octave 353 - 500 MHz is
generated from a tuned circuit formed by C31, D5, and L6, the latter is only evident as a
thicker length of track on the PCB. . The base of TR7 oscillator is driven from the
centre tap of L6 and the collector via C37 and R34, these components are positioned so as
to be mutually coupled to the oscillator tuned circuit.
70. R32,R33,C33 and C34 control the impedance of oscillator TR7 and compensate for: —
unwanted internal phase shift within the transistor. Having resistors in both emitter and .
collector circuits also prevents the formation of parasitic resonance which would other-—
wise occur via the transistor’s junction capacitances. i
71. Tuning of the oscillator is carried out by the varactor D5 with bias applied via L5.
The LE end of the oscillator range may be adjusted by C31 for 2 V at 353 MHz. The HF
end of the range should be approximately 15 V at 500 MHz. Output is taken from a low
tapping point on L6, via R27.
72. The lower half octave oscillator 250 - 352 MHz operates in a similar manner with
the capacitor values doubled in the tuned circuit to give the half—octave reduction in
frequency.
73. Selection 353 — 505 MHz (HIGH) and 250 — 352 MHz (LOW) is carried out by the
OSC HIGH control line (PLAD pin 10) from A2/2 Control circuit. When this is asserted
‘high’ TRS and TR6 conduct and complete the -12 V supply line to allow TR7 to conduct.
When the OSC HIGH control line is at logic ‘low’ TR8 and TR9 conduct and TR10 is
powered. Because only one oscillator is powered at a time from the single control line,
outputs are resistively summed at the input of IC7 amplifier. Both oscillators and
amplifier are mounted within the on-board screening so as to achieve a very low level of
load reaction.
46881-891U
4-18 Oct. 88
TECHNICAL DESCRIPTION
Frequency dividers (62.5 — 250 MHz)
74. The VCO output range (250 - 500 MHz) is divided into three paths via IC8, IC9 and
IC10 buffer amplifiers. IC8 provides the signal path for the 250 - 500 MHz range, IC9
the 62.5 - 250 MHz range and IC10 provides a synchronizing output to AA1/1 pro-
grammable dividers.
75. Selecting of the required signal path is controlled by IC4-IC6 signal gating circuit.
The control data is input via PLAD pins 6,7 and 11 and is shown on the circuit diagram as
range control logic and uses the letters (A) to (G) to indicate where assertion of data
(negative true logic) is made.
76. The output from IC9 drives two binary frequency dividers ICila and 1IC11b. These
D type flip-flops are wired as two binary dividers by connecting the Q outputs to their
respective D inputs. The first divider is clocked via pin 11. Both Q and QL outputs are
utilized, driving opposite ends of T1 balancing transformer. The output is taken from a
third winding via D15 when control logic line (B) is asserted. This arrangement gives a
symmetrical output waveform containing little second harmonic therefore simplifying
filtering.
77. When (B) is asserted ‘low’ R59 and R61 provide bias to allow ICila divider to
operate. R58 and R60 provide bias to the clock inputs via L16 and L35 to maintain these
at the mean logic level. The second divider operates when the bias provided via R78 and
R79 is applied, this occurs when both (A) and (F) are asserted ‘low’.
46881-891U |
Oct. 88 4-19
TION
TECHNICAL DESCRIP
. 88
46881-891U
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4-20
TECHNICAL DESCRIPTION
78. 250 - 500 MHz. When frequencies in this range are selected, point (E) is taken ~
dow’ turning D8 and D9 on and D10 off. (F), (A) and (B) are taken ‘high’, disabling
IC11a,b dividers; D11 is also turned off. The signal path is then routed from IC8 and
through a 500 MHz low-pass filter comprising L10,L11,C60-C62. Cut off frequency of
this filter is 750 MHz enabling signals of up to 500 MHz to pass but none of the third or
higher harmonics. A further tunable notch filter L12,L13,D12 and D13 eliminates the
second harmonics in the range 500-750 MHz.
79. 125 - 250 MHz. When frequencies in this range are required, point (E) is taken
‘high’, D8 and D9 are turned off and D10 is turned on. Points (F) and (B) are taken
‘low’ activating IC11a first divider. D11,D14 and D15 are also turned on and D17,D18
are turned off. The first divider’s output is routed via D15 and D14 to a 250 MHz
low-pass elliptic filter comprising L14,L15, C63-C67. Cut off frequency of this filter is
375 MHz so the required range is passed but the third harmonic in the band 375 — 750
MHz (and higher harmonics) are eliminated. The signal is then routed from the low-
pass filter via D11 to the input of the 500 MHz low-pass filter to be combined with the
250 — 500 MHz signal frequency range.
80. 62.5 -125 MHz. When frequencies in this range are required, points (A) and (F)
are taken ‘low’ and (B) is taken ‘high’. D15 is turned off, D16 and D18 are turned on,
both IC11a and IC11b dividers operate and the output (62.5-125 MHz) is taken from T4
transformer secondary. The signal is passed through a 125 MHz low-pass filter 21,
L22,C87-C91. Cut off frequency of the filter is 187.5 MHz to eliminate the third and
higher harmonics. This allows the required 62.5-125 MHz band to be routed via D16 to
the 250 MHz low-pass filter L14,L15. The signal is then combined with the 125-250
MHz and the 250-500 MHz signal paths as far as the junction C71,D20,D21.
81. At C71 the signal paths divide. When signals in the range 62.5-500 MHz are
selected, point (C) is taken low and point (D) is taken ‘high’, D20, D23 and D31 are
turned on and D32 is turned off. Signals are routed to the input of the HF output
amplifier stage via D20,D23,D31 and C102. :
Frequency doubler (500-1010 MHz)
FROM VCO
250-SO0MHz AMPLIFIER
Cc
Fig. 4-9 Frequency multipliers, simplified block diagram (AB1/2)
82. The frequency range of 500-1010 MHz is obtained by taking the VCO output range
(250-500 MHz) from the output of the 500-1010 MHz notch filter and following this with
a frequency doubler circuit. Selection is effected by the assertion of the range control
logic, point (C) is taken ‘high’ and point (D) is taken ‘low’. 20 is turned off and the
signal path is then taken via the amplifier IC13. Output from IC13 is detected by D24
which drives an automatic level correction circuit. This controls the RF resistance of
D21,D22 and thus the drive to the doubler circuit.
46881-891U
Oct. 88 4-21
TECHNICAL DESCRIPTION
83. The frequency doubler circuit comprises T5, balancing transformer and D27—D30
diode bridge. Insertion loss of the doubler is compensated for by IC3 which provides 12
dB of amplification. This output is filtered by a 500-1010 MHz voltage tuned band-pass
filter comprising D34-D37 and T6.
84. The filter together with the 500-1010 MHz voltage tuned notch filter previously
described share a common control line. This originates from a digital-to—analogue
converter on A2/2 board via PLAD pin 15. Tracking data is set by the requirements of
the band-pass filter which has no other means of adjustment. The notch filter is then
aligned to this data by adjustment of L13. Output from the 500-1010 MHz band-pass
filter is connected via D32 and C102 to the HF output amplifier.
HF output stage (62.5-1010 MHz)
| =TR19,TR20 |
CONTROL
po eS) 4
| CONTROL |
| 1R13,D38-D41|
(LOOP AMPLIFIER}
IC15
FROM A2/2 DETECTOR
CORRECTION CCT.
{LEVEL}
PLAD/3
Fig. 4-10 HF output stage (62.5-1010 MHz) simplified block diagram (ABI/2)
85. The HF output amplifier stage comprises TR19 and TR20 together with D43 output
detector, loop amplifier IC15,TR13, and pin diodes D38-D41. The stage is required not
only to provide levelled output over the range -7 to +10 dBm but also amplitude
modulation of up to 80%. The total dynamic range of the ALC is thus +10 to -21 dBm.
AM is specified using carrier frequencies up to 400 MHz although the circuit is usable to
1010 MHz.
86. The RF reference level is fed to IC15 pin 2 via D42. D42 and D43 are in close
thermal contact and operate at similar bias currents so that the voltages dropped across
the diodes are accurately matched. IC15 pin 6 goes negative turning on TR13 and
- [238-D41. The RF output of the amplifier IC14 pin 8 rises until the peak voltage
detected by D43 equals the reference voltage. When AM is in use the modulating voltage
is superimposed upon the reference. This is performed on A2/2 board and is described
in that section.
or Pay
87. The levelling achieves a defined RF voltage at the input of R123 which provides a»,
50 Q@ source. The output is then fed to relay RLA where point (G) range control logic ©
selects either this output or the output from the BFO system.
46881-891U
4-22 Oct. 88
TECHNICAL DESCRIPTION
96. A mimic detector, D44 and C110 peak detects the combined level and AM signal
arriving at PLAD pin 3. As the AM is added the RF level reference voltage at the
junction of R105, R106 increases due to the action of D44. Since the reference and AF
detected levels are summed at IC12 pin 6 the AM induced level error is cancelled out.
97. At low modulation frequencies the detector output will decay between envelope
peaks at a rate depending on its time constant. In order to preserve the AM the reference
voltage applied to the error amplifier must match the RF detector voltage exactly. If this
is not accomplished IC12b error amplifier will produce a control signal that will tend to
remove the AM from the RF signal. To make the reference behave in a similar manner
as the AF detector voltage the mimic detector is set to have the same time constant as the
RE detector.
98. The two detectors are of opposite polarity and C104 provides a long time constant to
give a DC output from IC12b that is a measure of the error in carrier level irrespective of
whether AM is in use or not. This is fed back to the current-controlled attenuator to set
the level of signal at the mixer input such that the output level is correct. In common
with the HF output amplifier, the signal is levelled as a voltage and R122 gives a source
impedance of 50 Q.
46881-891U
Oct. 88 1
TECHNICAL DESCRIPTION
POWER SUPPLY/CONTROL (A0/1 and A2/2)
Circuit diagram : Figs. 7-2, 7-4 & 7-5
99. The primary purpose of this board is to interface and control the various areas of
the instrument that require access to the microprocessor via the internal instrument bus.
There are three main areas on the board, analogue control, digital control and power
supplies. These are described as follows:—
Power supplies. Four stabilized voltage lines are derived. These are +24 V, +12 V,
+5 Vand -12 Vd.c. The +5 V rail chiefly supplies digital ICs. This is generated
using discrete circuitry. The +12 V and -12 V rails supply a number of amplifiers
and use monolithic 3-terminal regulators. A +24 V rail is used for low current
purposes and is generated using a voltage doubler.
Digital control section. Interrupts are controlled and routed to the microprocessor.
A serial bus from the microprocessor is converted to an 8-bit parallel format which
is then fed to latches on both A2/2 board and other boards. Address lines are also
decoded on this board. The display drives on A1/2 board are supplied with a
special format serial bus from A2/2 and data appearing on the 8-bit data bus can be
converted back to serial data for transfer to the microprocessor.
Analogue control. This area has several functions as listed below. Control data
for each of the operations is routed via the 8 way bus:-—
(1) Modulation signal ALC
(2) Modulation depth or deviation control
(3) RF level control
(4) RF filter tuning
(5) Reverse power protection
(6) Attenuator drive
(7) Jitter correction drive
Power supplies
100. The AC mains supply range is set by two selector switches, SB and SC whose
position is locked by a reversible locking plate. Supply transformer T1 and fuses FS1,
FS2 are mounted on the rear panel assembly which can easily be hinged to provide
access.
101. +5 V supply line. A0/1 T1 secondary 2 is used to supply rectifiers D1 and D2 via
PLE pins 1,3 and 4. A2/2 IC3 controls the +5 V rail providing both short circuit current
limiting and stable voltage regulation. A voltage reference diode, D10 provides a stable
reference point on the resistor chain R12-R15 against which the sense point (junction of
R19/R20/R112) is compared. R15 is adjusted for 5.1 V +0.1 V.
102. If the sense voltage at R19/R20/R112 is greater than the reference voltage at the
junction of R13/R14 IC3a output reduces and so does the drive to A2/2 TR1 base. R3
and R11 set the maximum permissible current limits for A2/2 TR1 collector and base
respectively. A0/1 TR1 and A2/2 TR1 form a super beta pair with control of A2/2 TRI
base effectively setting the operating point of A0/1 TR1. The emitter of A0/1 TR1 is
connected via R19 to the sense point so that reducing the current flowing into A2/2 TRI
base, current flowing through A0/1 TR1 also reduces. The voltage across the load will
then fall to cancel the initial increase of sense voltage. This negative feedback system
will equalize the voltage at the regulator output and at IC3a pin 3 to a nominal +5 V.
46881-891U
4-26 Oct. 88
TECHNICAL DESCRIPTION
103. C49,C39 and R105 improve the transient response. Current limiting is achieved by
monitoring the voltage drop across series resistor R19. Resistors R17 and R112 apply
this voltage to IC3b. If due to excess current, the voltage at the junction of R16,R18 and
R17 exceeds that on R112, then IC36 pin 7 will go negative, depriving A2/2,TR1 of base
current by drawing it instead through R10 and D9. This will restrict the current flowing
into the load.
104. In order to visualize the current limiting that occurs consider R16/R18 as a Thevenin
equivalent (9.09 kQ down to -1.09 V) and note that no current flows into IC3b pin 6. As
the voltage at pin 5 falls, a lesser voltage at the top of R17 will be sufficient to bring the
voltage of IC3b pin 6 up to equal that of IC3b pin 5. This implies a lower voltage across
R19, i.e. the overall regulator current limit goes down as the output voltage goes down.
This reduces short circuit dissipation in A0/1 TR1. However to provide assistance when
fault finding, it is preferable to have some current flowing even under abnormal load
conditions. The short circuit current is therefore deliberately not equal to zero.
105. +12 V supply line. A0/1 T1 secondary 1 winding is used to supply the bi-phase,
rectifier D3 which in turn charges C2. A0/1 IC1 and resistor chain A2/2 R4-R6 provide
a +12 V regulated output with short circuit current limiting and over temperature pro-
tection. The voltage at PLH pin 5 is approximately 1.3 V below that at PLH pins 6 and 7
and the regulator A0/1 IC1 compares the voltage sensed at pins 5 and 7 with an internal
bandgap reference. Current then flows out from the regulator via PLH pin 6 until the
voltages equalize. PLH pin 7 receives a separate sensing signal from the regulator to
improve the load regulation. D5 protects A0/1 IC1 from positive voltages on PLH pin 6
when PLH pin 4 voltage is low. C9 improves the ripple rejection.
106. -12 V supply line. Voltage in this circuit is generated in an identical manner to the
+12 V supply except that the components are mounted on A2/2 board. One additional
component, R108 is fitted to dissipate some of the heat generated and allow a smaller
heatsink clip to be fitted to A2/2 IC1.
107. +24 V supply line & voltage doubler circuit is used to obtain this low current supply
rail which is obtained via A0/1 T1 secondary 1 winding. All the components of the
doubler circuit are mounted on A2/2 board. Consider the charge on C3; when the
voltage at PLF pin 7 falls below zero C3 is charged through the lower left-hand diode of
bridge D4.
108. When the positive phase of A0/1 T1 begins, the positive charge on C3 will start to
charge C6 through the upper left hand diode of bridge D4. If little current is drawn the
charge on C6 will remain and eventually the voltage across it will build up to the peak
output from A0/1 T1 and in addition the peak voltage developed across C3 i.e. approxi-
mately twice the peak output of A0/1 T1. C4 charges C6 during the negative cycles of
AO/1 T1.
109. C2 regulator is similar in its operation to A0/1 IC1 with resistor chain R7-R9, R8
providing the means of adjustment to +24 V +0.25 V.
46881-891U
Oct. 88 4-27
TECHNICAL DESCRIPTION
Digital control section
110. The circuit shown in Fig. 4-12 below illustrates how the microprocessor com-—
municates with all the instrument latches, other than those on the synthesizer board. It
does this over a serial bus which is converted to, and from, parallel data.
_ . y TO AL/2 8 BIT
c/D SCKL DATA i peters DATA BUS A
CONTROL
ABR AGI: | 1c29-1C31
DECODER
s /B
18 ADDRESS
| LINES
| c 8 | i t
GPIB
REGISTERS
ADDRESS
nd Ic9
CLOCK
FROM_ LP
via (E)
STROBE
FROM [LP
el
SERLAL
BUS
Fig. 4-12 Data conversion, simplified block diagram (A2/2)
111. Serial to parallel conversion. Serial data is initially fed to IC5, pin 2 DATA input,
shift register and is clocked in on the positive edge of the CLOCK input at ICS pin 3.
After eight bits have been entered, IC5 output Qs begins to change state; IC5 at this point
acts like a delay unit eight clock cycles long i.e. data entered on the D input via ICS pin 2
appears eight cycles later at Qs. It is also possible to transfer data that is clocking
through on to the outputs Q1 - Q8. This is done by taking the STROBE line to logic
‘high’. IC7 and IC9 are identical to IC5 in operation.
112. Since the clock inputs of IC7 and IC9 are gated (using IC6b and c) to IC5 outputs
Q1 and Q2 respectively, ICS must be loaded with the appropriate control byte before the
data and address lines can be set. Having sent the first byte (containing data which will
be discussed later), three more bytes need to be clocked through to load IC7 and IC9.
The first will go direct to IC9, the second to IC7 and the last to ICS.
46881-891U
4-28 Oct. 88
TECHNICAL DESCRIPTION
CONTROL (ICS5) DATA (IC7) ADDRESS (ICQ)
; ; Tre i ; vee
cpp ON/C LATCH
CLOCK ENABLES 8 BIT DATA
A
REGISTERS ADDRESSES
RD TO GPIB
OR A/B TO 8- BIT DACS
OR C/D TO DISPLAY DRIVES
Fig. 4-13 Serial data string (A2/2)
113. The control latch, IC5, sends information to one of three possible destinations:
(a) Serial data for the display goes via the Display Data Converter (IC8).
(b) 8-bit bytes for the keyboard and GPIB are sent via Data Converter IC7.
(c) Outputs Q1 to Q5 of Address Converter IC9 drive a Register Address decoder |
consisting of IC29-31 which provides address and control signals for various d-a
converters and other devices on the A2/2 board.
Note that pin 7 of ICS provides a strobe line for the Register Address Decoder.
114. If display data is required it has to be converted back into serial form before being
sent to A1/2 display drivers, IC1 and IC2. However a variety of command data is
required when the display is initially set at switch on and the differentiation is made by
taking IC5, Q8 ‘high’ instead of ‘low’. One of IC30’s outputs will be taken ‘low’. Data
will be accepted on the returning positive edge.
115. Parallel to serial conversion. To change from parallel to serial format an 8-bit
shift register, which may be pre-loaded, is used (IC8). Data present on inputs D0 - D7 is
clocked out on Q8 and either sent to the display, in which case TR3 is switched on (Q6 of
IC5 held ‘low’), or sent back to the microprocessor. In the latter instance IC5,Q6 is held
‘high’ and TR4 acts as an inverter. C17,R24 and IC4 act as a monostable with an output
duration of approximately 10 ys. This is triggered on a negative-going edge of the
STROBE line. When the STROBE line is asserted ‘low’, parallel data is forced into IC8.
This may then be clocked out by taking IC5, Q3 ‘high’. The use of a single clock ensures
that the clock edges and the data are synchronized.
116. Interrupts. The microprocessor will normally be executing a ‘zero task’ whilst the
instrument provides the output signal requested. If a change is required it must first be
interrupted and then be made to respond according to the new information presented.
The interrupts may be from any of the following four sources:
GPIB
Keyboard
Reverse power protection system
Modulation signal automatic levelling loop, i.e. signal too high or too low.
46881-891U
Oct. 88 4-29
TECHNICAL DESCRIPTION
117. GPIB interrupt (High priority). IC4e pin 3 will be asserted ‘high’ causing a
negative-going edge to be sent to IC12d pin 12 and asserting IC13 pin 12 ‘low’. IC12d
pin 13 will normally be at logic ‘high’ and IC12d NAND gate will function as an inverter
causing a positive edge output to occur at the output on pin 11. This is then fed as the
INTERRUPT line via PLL pin 13 to AA2/1 microprocessor. R25 prevents spurious inter-
rupts if the GPIB is not connected. The microprocessor will react by addressing IC13
latch and reading D3 and D4 outputs to determine whether it is GPIB or keyboard
requesting the interrupt. The microprocessor will then execute the necessary tasks to
accept incoming data.
118. Keyboard interrupt (High priority). Action here is the same as described above,
IC6d pin 12 goes ‘low’ IC6d pin 11 also goes ‘low’ creating a positive edge on IC12d pin
Lt.
119. Reverse power protection system interrupt. Relay AC1 RLF is normally energized
when the instrument is switched on. Should there be an accidental application of reverse
power AC1 RLF will trip. A2/2,TR16 is turned off and IC12c pin 8 will go ‘low’. IC12c
pin 9 will be ‘high’ therefore asserting IC12c pin 10 ‘high’. This will cause IC4f pin 4 to
go ‘low’ causing a positive edge on 1C12d pin 11. Pin 12 is held ‘high’ and a positive
edge INTERRUPT pulse will again be created on IC12d pin 11 and routed to the
micro-processor via PLL pin 13. To monitor keyboard interrupts (those required to reset
the RPP) the outputs of IC13 are scanned. If a change is detected the normal keyboard
reading sequence will occur but only RPP will have any effect. GPIB interrupts are also
dealt with using the scanning process.
120. Modulation signal automatic levelling loop (ALC) interrupt. If the modulation
signal applied is of a level that takes the control system outside preset limits (0 V and -6
V on IC15b pin 8) an interrupt will be caused. If the modulation level is insufficient,
IC12a pin 1 will go ‘low’ and pin 3 ‘high’. IC12b pin 6 will normally be set ‘high’ thus
pin 4 will go ‘low’. IC12c pin 10 is then set ‘high’, IC4f pin 4 is sent ‘low’ and as before
a positive edge on IC12d pin 11 INTERRUPT line is created. A similar action occurs if
the modulation signal is excessive. This is the only interrupt that can be masked and this
is carried out by setting IC11 Q3 ‘low’. If an interrupt from this system is read the
microprocessor will periodically assert IC11 Q3 ‘high’ and check to see if the modulation
signal is within the specified limits.
Analogue control
121. Modulation signal ALC. This system is always in operation when the instrument is
selected to INT MOD but can be selected in or out with the front panel MOD ALC key
when in EXT MODulation mode. MOD ALC on is indicated by an LED adjacent to the
key. The internal modulation signal is routed through RLA by taking IC11 QO ‘high’.
R29 provides an approximate 600 Q source impedance for the MOD IN/OUT front panel
socket SKA.
122. IC15 is configured as a non-inverting amplifier with resistors R113 (adjust EXT
MOD), R38, R35-R37 providing a feedback potential divider chain. TR6 is switched on
via IC11 Q2 if MOD ALC is not required, this also switches TR7 off to give a fixed gain
of nominally 3.54 from the circuit. If MOD ALC is selected TR7 then provides the
mechanism for varying the gain of the stage by using it as an approximation to a voltage
controlled resistor.
46881-891U
4-30 Oct. 88
ne
TECHNICAL DESCRIPTION
123. D14,C25 peak detect the output signal which is used as an offset against a negative
voltage produced by R44,R45 and D15. Both voltages are summed at IC15 pin 9 and if
the result is not zero then the output of IC15, pin 8 will integrate up or down charging
C26. If 1IC15 pin 8 output were to increase (due to a low level signal at IC15 pin 7), then
TR7 gate would also increase via R40 to turn on TR7 (R39,C24 improve the control/signal
isolation).
124. When TR7 turns on its resistance between drain and source reduces and the gain of
the stage increases. The output of the amplifier then goes up by a corresponding amount
to give the required increase in output voltage. D16 improves speed by preventing C16
charging beyond +0.6 V. When the gate of TR7 is at 0 V, TR7 will be fully on - normal
control is usually —3 or -4 V.
125. TR7’s control voltage is monitored by IC18a and IC18b. _ If the level goes
above 0 V IC18a’s output switches low causing a ‘LEVEL LO’ interrupt. If the level
goes below -6 V then IC18b output decreases and a ‘LEVEL HI’ interrupt is generated.
It will simultaneously increase the signal level required for levelling at IC15a, pin 7. This
hysteresis prevents multiple interrupts caused by a low frequency input signal whose level
may be at the point of being just too high.
126. Modulation depth/deviation control. Three forms of modulation are possible AM,
FM, or ®M. These are controlled by three dual, digital-to-analogue converters (DACs).
Both absolute level and calibration data are entered using these digital-to-analogue
converters.
127. Combining Auxiliary, External and Internal modulating signals. The required
combination of internal, external and auxiliary modulation is summed as shown in Fig.
4-14 and the resultant waveform is sent to the reference voltage pin (Pin 4) of multiplying
DAC IC19.
iC32
Aux. Mod. input from PLX :
( 1Voit RMS )
10 Volts p-p
Ext. Mod. Input from PLJ 10 Volts p-p
— ee ( >— | >_> ( +} TO VREF
as of DAC
° IC19 Pin 4
1KHz Internal Mod. input
from PLL
Fig. 4-14. Combining Aux., Ext. and Int. modulating signals (A2/2)
46881-891U |
Oct. 88 4-31
TECHNICAL DESCRIPTION
Amplitude modulation above 62.5 MHz
wy +12V
| |
fj] DETECTOR
| N CORRECTION
: RgO
IC1IS{A) IC19{B} IC28(A)} |
& IC15c & IC15d & IC16c
SIGNAL y, }
10V p-p /? {> ) — : _, SIGNAL
FROM iC15a “| i ; 6 IC28(b) : PLM/3
GAIN GAIN e | | TO ABI/2
200 o-1 | ' Ic16d
a OFFSET ]
| = {| R83
= Ld
1 Re4 SET ALC LOW
-12V
Fig. 4-15 AM signal path >62.5 MHz (A2/2)
128. The series path shown in Fig. 4-15 requires four sets of data to provide the correct
signal. 1C19(A) is loaded with a number proportional to the AM depth requested and
1C19(B) has AM calibration data entered. 1IC28(B) will contain calibration data for the
RF level and finally IC28(A) holds a number equal to the RF output voltage in mV
(described in later paragraphs).
129. The AM depth is set by the ratio of modulation signal to DC level at IC28 input, pin
19. If the RF level is changed, the proportion of DC and modulation signal will stay
constant and therefore so will the AM depth. AM depth of modulation up to 99.5% may
be obtained for output levels up to +3.9 dBm but beyond this the combination of AM and
power level will be restricted to ensure that peak powers of greater than +10 dBm are not
requested.
130. If too great an AM depth is requested for a particular power level selected at that
time, the power is reduced and a colon is flashed in the RF LEVEL display indicating the
change and the new level selected.
131. The detector characteristic present on board AB1/2 is not an ideal one as can be
seen in Fig. 4-16. It is therefore necessary to apply correction. At low RF levels (on
AB1/2) the detected voltage rises with the square of the RF voltage. As the level
increases above approximately 20 mV, however, the relationship becomes linear.
132. Consider Fig. 4-16. If we wish to obtain half the RF voltage VRFA, simply halving
the reference voltage (and, due to loop action the detected voltage also, “ ), will result
in too low an RF level, (VRFB). For this reason the drive voltage must be greater at VB.
1C27 and its associated circuit provides the necessary detector correction. The circuit is
described in the following paragraph.
46881-891U
4-32 Oct. 88
TECHNICAL DESCRIPTION
DETECTED
VOLTAGE
VAS Se SS
RF OUTPUT
VOLTAGE
VREA
2
Fig. 4-16 RF detector law (A2/2)
133. Detector correction circuit. Two transistors in IC27 are used to pre-distort the
signal that drives the envelope feedback system on the RF board, AB1/2. This only
occurs at low voltage levels and the amount of shaping is determined by R90 (CORRECT
DET) and the potential divider chain R91 to R93. A common drive signal appears on
both transistor bases at pins 12 and 9 of IC27. The feedback signal comes from IC27 pin
13 via R85. R88 ensures that the left-hand transistor is never turned off but merely
provides temperature tracking of the diode characteristic of the right-hand transistor.
The latter actually introduces the square law characteristic. This modified AM drive
waveform is finally fed to the RF processing board AB1/2 via PLM pin 3.
Amplitude modulation below 62.5 MHz
134. To obtain the correct depth of modulation on signals below 62.5 MHz two drive
signals are required. The first driver provides a fixed modulation at PLM, pin 5 via
IC21b. The second driver ensures that the RF level reference that is ultimately applied to
AB1/2 comparator is increased by an amount equal to the detector voltage increase due to
the AM. If this is not achieved there will be a shortfall in RF level.
135. Fig. 4-17 shows the signal path for the two AM drive signals. IC21b provides the
drive for the fixed frequency modulator. The gain of this stage is such to allow the full
100% modulation. Depth is set by data entered into the digital-to—analogue converter
IC19(A), and calibration data is entered via IC19(B). R111 prevents capacitive loading
affecting IC21b.
136. The modulation signal is also fed via IC14c and IC16b through IC28 and uses the
same signal path as signals above 62.5 MHz but in this case the square law transfer
characteristic is no longer of any consequence.
46881-891U |
Oct. 88 4-33
TECHNICAL DESCRIPTION
ICTS(A) 1C19(B) IC28(A) IC28(B)
& IC15c & 1C15d & IC16c & IC16d,IC27
MOD
SIGNAL
10V p-p
FROM ic15a
) TO ABI/2
e RF PROCESSING
1 BOARD
IC21b
>
GAIN
x2.4
Fig. 4-17 AM signal path <62.5 MHz (A2/2)
Frequency modulation
= PLM/5
137. In order to obtain the necessary low modulation frequency response on FM, two
signal paths are used. One path drives the VCO tuning line whilst the other is used to
modulate the phase of the reference signal used in the 250 — 500 MHz phase locked loop
(PLL). If the second path was not included the action of the PLL would be such that
where the modulation frequency is below that of the loop bandwidth (200 Hz), it would be
removed from the RF signal.
IC19{A} 1C19(B) 1C20(B)
& IC1Se & IC15d & IC21a
TO AB1I/2VCO
PLM /12
TUNING LINE
IC20(A)
ICifa Ici?b
TO AAI/1
REFERENCE
PLL/16
PHASE
MODULATOR
GAIN INTEGRATOR
@ ii, 1Hz CUT OFF
Fig. 4-18 Dual path FM drive (A2/2)
138. VCO tuning line drive. IC19 DAC changes the drive level according to the peak
deviation requested. IC19(A) is loaded with a number proportional to that deviation
whilst IC19(B) has a multiple of 6 which changes according to the carrier frequency
selected and maximizes the resolution of IC19(A).
TABLE 4-1 DAC VALUES FOR VARIOUS FM DEVIATIONS (A2/2)
Deviation Value in DAC
0 -— 249 Deviation
250 -— 499 Deviation +2
500 - 999 Deviation +5
1000 -1999 Deviation +8
2000 -—3999 Deviation +16
4000 -7999 Deviation ~32
46881-—-891U
— Oct. 88
nM
TECHNICAL DESCRIPTION
139. Table 4-1 shows how a resolution of 0.4% of full-scale deviation is achieved. IC16a
has a gain set by R50/R51 or R52/R53 dependent on the value of deviation selected. For
values less than 10 kHz it is x0.18 and for deviations between 10 - 100 kHz it is x1.8.
MOS switch IC14 effects the change of gain via two output lines from IC11, Q4 and QS.
Control data on these lines are shown in Table 4-2. Virtual earth switching ensures that
the resistance of the switch when on has negligible effect on the gain of the stage.
D22,D23, ensure no distortion occurs when a channel is not in use. R31 and R32 provide
the correct bias level for IC14 switches.
TABLE 4-2 DECODING OF FM/®M FUNCTIONS (A2/2)
IC14
Q4|Q5 Function
0 0 FM 0 —- 9.99 kHz
0 J ®M 0 - 9.99 rads
1 O FM 10 - 99.9 kHz
1 1 Not used
140. IC20(B) is fed from IC16a and the non-inverting input on the associated IC21a,
pin 3 is taken to ground on board AB1/2 via PLM, pin 2. This minimizes spurious
modulation caused by induced voltages.
141. Reference phase modulator, low FM path. This second path drives a phase
modulator on board AA1/1. To obtain an equivalent frequency modulation the
modulation signal must be applied through an integrator. To consider why this 1S
necessary, imagine the effect of a steady voltage being applied to the modulator.
Without an integrator a steady phase error would be created. With the integrator
however, an increasing phase error with respect to time will occur and this gives the
required frequency shift.
142. To maintain the correct loop operation the modulation of both the VCO and the
reference phase signal must be identical therefore producing no error signal at the output
of AA1/1 main synthesizer phase detector. To this end IC20(A) is loaded with data that
is proportional to the frequency at which the 250-520 MHz synthesizer is operating. As
the synthesized frequency increases, the ratio of deviation to synthesizer frequency
reduces and a smaller phase change at the phase detector will cancel it out. The
reduction of gain in IC20(A), due to its configuration, will track this requirement.
143. The ‘SET LF FM’ potentiometer R58 and resistors R57, R59 ensure that the above
described correction can be attained. Correct setting of R58 will ensure a substantially
flat frequency response from less than 10 Hz to well above 25 kHz.
144. IC17b with its associated circuit forms an integrator with a low frequency roll off at
approximately 1 Hz. DC feedback is maintained through R71, R72, R62 and R64 and
the integrating action is given by R63 and C33. The low frequency cut-off is due to the
input coupling capacitor C32 and feedback decoupling capacitor C40. The integrated
signal is fed to AA1/1 via PLL pin 16. In order to optimize the response of low frequency
square waves the overall amplitude response of IC17b circuit actually has a slight rise
around 1 Hz before dropping off below this frequency at 12 dB/octave.
46881-891U
Oct. 88 4-35
TECHNICAL DESCRIPTION
Phase modulation
IC19(A) 1C19(B) IC20(B)
RICiSc &ICISd ICiéa & IC2Ia
GRA: TO AB1/2VCO
PLM/12
10V p-p = ;
FROM IC15a TUNING LINE
GAIN
APPROX. 0.5-1
1C20(A)
IC17a
r
GAIN INTEGRATOR
@ li, 1Hz CUT OFF
Fig. 4-19 Phase modulation signal path (A2/2)
TO AAI/1
REFERENCE
PLL/16
IC17b
PHASE
MODULATOR
145. Since this is ‘angle’ modulation, like FM, the signal path is similar to that described
in the frequency modulation paragraphs previously. The only difference being that IC16a
is converted from a gain stage to a differentiator providing a 6 dB/octave pre-emphasis.
R55, R56 and C29 are set for the main time constant whilst R54 restricts the gain at high
frequencies to reduce noise in that area. R56 ‘SET ®M’ allows calibration of the system.
RF level control
IC28(A) 1C28(B)
ic16C Ic16d
TO AB1/2
PLM/3
RF PROCESSING
Nf R84 “SET ALC
LOW"
-VE
VOLTAGE
Fig. 4-20 Simplified RF level control signal path (A2/2)
146. This control circuit is used over the complete carrier frequency range. RF processing
board AB1/2 requires a voltage that approximates to an offset plus a variable voltage that
is dependent on the RF level requested. The square law consideration discussed in the
AM modulation paragraphs is of little importance for simple level changes because the
range is limited from -8 dBm to +10 dBm. The voltage at PLM pin 3 must correspond to
approximately twice the actual peak RF level requested due to the 50 Q source resistor on
board AB1/2.
147. IC16b with R70 and R74 provide a constant voltage of -1.6 V. C52 decouples the
reference line to ground. Data is entered into the digital-to-analogue converter, IC28 in
one of two formats. For RF output levels below +2.9 dBm, a number proportional to the
output voltage is sent to IC28(A) whilst a calibration value (which could be up to 25519) is
entered into IC28(B).
46881-891U
4-36 Oct. 88
TECHNICAL DESCRIPTION ©
148. If the RF level requested is greater than +2.9 dBm, then the value in IC28(A) is
‘reduced by a factor of ¥10 and the calibration value is increased by the same amount.
149. R84 ‘SET ALC LOW’ and R88 allow the required offset to be introduced. This is
effected at Pin 9 of IC27. The DC level is then transferred to AB1/2 via the base emitter
junction of the right-hand transistor of IC27, potential divider R91, R92 and PLM pin 3.
RF filter tuning
150. Two tracking filters are used on board AB1/2. One is a notch used to reduce the
second harmonic component of the oscillator output; the other is a band-pass filter used
to reduce unwanted components on the doubler output. The latter has no means of
adjustment and so calibration data is entered into A2/2 IC23(B) to ensure that the
band-pass filter operates at the correct frequency. The notch filter is then adjusted to
reject the second harmonic of the oscillator output with the oscillator set to its lowest
operating frequency (250 MHz). The tuning law of the band-pass filter and notch are
sufficiently alike to allow the same tracking data to be used in both cases.
151. IC23, pin 18 is coupled to the -12 V line, this is inverted and then multiplied by
1C17d. TR13 ensures that the maximum tuning range is available, allowing PLM pin 15
to be taken to within 0.5 V of the +24 V rail. R80, R81 provide the correct bias for TR13
and R82 increases the gain of IC23(B) from x1 to approximately x2.
Reverse power protection switching and attenuator drive
152. IC22, IC18c and IC18d with their associated circuits control the operation of AC1
attenuator relays. Latch IC22 is fed with data dependent on the level of fixed attenuation
required, details of which can be seen in Table 4-3.
TABLE 4-3 ATTENUATOR SWITCHING LOGIC (A2/2)
Attenuation QO Qi Q2 Q3 Q4
ODOR FP OR FR OR HOHE
=a Oem Ome OFM me © mr
oo oo oOo 0 OC HM eH Ree
ON
©
oQoQoooc°coooo oF fF ms
DOO 0 FR Ree ee Se ep
0
153. When the required selection is made the respective Q output line(s) are grounded
and the associated transistor (TR8-TR12) is turned on. Base current flows via the load
resistors (R75-R78) and diodes D17-D21 protect the transistors from the large
negative-going inductive spikes created when the relays are turned off. Relay current
flows via PLN pins 2-7. Thus if a particular pad is required current is supplied to that
pad’s relay.
46881-891U
Oct. 88
TECHNICAL DESCRIPTION
154. IC18c and IC18d are comparators monitoring the voltage levels present on the
attenuator. If PLN pin 9 voltage should exceed +0 .04 V (when a voltage overload is
applied to the RF OUTPUT socket) IC18c will switch its output to a high level. D24 and
D26 then conduct and turn off TR16. This in turn will cause the RPP relay AC1 RLF to
drop out and at the same time initiate an interrupt, RPP TRIPPED L, to the micro-
processor. This would be in the form of a logic ‘low’ level applied to IC13 pin 6 via
R104.
155. Similarly, if a negative voltage overload is applied to the RF OUTPUT socket this
will cause PLN, pin 10 voltage to fall below _0.04 V. IC18d output will be set ‘high’ and
again TR16 will be turned off via D15, D26 and R101. R103 ensures that the energy
stored in the RPP relay is dissipated in the least time possible.
156. RPP reset. If either IC18c or IC18d output goes ‘high’, R100 pulls the comparison
level of IC18d above 0 V. Since AC1 negative detector D2 will be unable to reach this
level IC18d would remain at logic ‘high’ output even after the overload is removed. It is
therefore necessary to apply an external reset. When the RPP is tripped the keyboard is
disabled with the exception of the RF LEVEL key. The REV PWR annunciator will flash
on the RF LEVEL display to indicate the presence of an overload. No further keyboard
operation can be made until the RPP is reset by pressing the RF LEVEL key.
157. On pressing the key IC22, Q5 output will be set from ‘low’ to the ‘high’ state, the
positive edge is transferred via C38, to the junction of R96, R97. If the magnitude of the
detected voltage is less than 40 mV IC18d output will change from ‘high’ to a ‘low’ state
and TR16 will again be turned on. AC1, RLF energizes and normal operation is resumed.
If the overload is still present IC18d output will remain ‘high’ and the RPP will not reset.
Jitter correction drive
158. In order to reduce phase jitter of the carrier frequency which is introduced by the
fractional N technique, an offsetting phase error is required. A circuit on the Synthesizer |
board AA1/1 generates this but a reference voltage, inversely proportional to the synthe-
sized frequency is required. 1C23(A) and its associated circuit provide this function.
159.-R66, R68 and R67, CORRECT JITTER, provide an adjustable reference that feeds
digital-to-analogue converter IC23(A). ICi7c and IC23A are configured to give a gain
that is inversely proportional to the value of data entered into the digital-to—analogue
converter. The eight most significant bits of the synthesizer frequency are entered into
the digital-to-analogue converter and thus the output of IC17c pin 8 will be a voltage that
goes down as synthesizer frequency goes up. It is sent to AA1/1 via PLL pin 1 as the
JITTER CORRECTION REF.
4688 1-891U
4-38 ”
TECHNICAL DESCRIPTION
DISPLAY AND KEYBOARD (A1/2)
Circuit diagram : Fig. 7-3
160. The keyboard facilitates instrument operation by interrupting the microprocessor
(through a priority tree) which runs an interrogation of the keyboard matrix to locate the
switch selection. The microprocessor then runs a new task appropriate to the key(s)
pressed. Information giving the current state of the instrument is continually displayed
and includes frequency, RF level and modulation.
161. Data is displayed on a combined two phase multiplexed liquid crystal display
(LCD). Eight light-emitting diodes (LEDs) are also used to indicate the function
currently selected. Three light-emitting diodes are dedicated to displaying the currently
selected internal modulation frequency. Two specialized integrated circuits convert
serially transmitted information into the waveforms required to drive the LCD. Drive
information for the LEDs is provided by 8-bit latches.
Keyboard operation
162. Switches are arranged in a six—by-six matrix and are connected in rows to IC3 data
latch. Initially the rows are set to a logic ‘low’ level. The columns of the matrix are
connected to R9 pull-up resistors, which initially set all the columns to logic ‘high’ level.
One of the resistors, R9(h) is a pull-up for D9-D14 six input gate. This gives an OR
function using negative logic convention.
163. The columns drive both the six input gate and ICS data latch. ICS controls the data
bus via SKK pins 5-8 and 13-16. When a key is pressed a connection will be made from
the column that the key is in to the row that the key is in. This causes the column to be
asserted ‘low’ because all of IC3 Q outputs are held logic ‘low’. A connection from the
diode gate is also made to the microprocessor via SKK pin 11. This line KEYBOARD
INT L when asserted ‘low’ causes the microprocessor to commence running a new task.
This will in turn assert all but one of IC3 Q outputs logic ‘high’; each output in turn then
reverts to logic ‘low’ commencing with QO. As this occurs the columns are monitored by
ICS.
164. If the 6-bit word being output by the matrix is not all ‘1’s then the word is digitally
rotated to find which column has a logic ‘low’ on it. The combination of row and column
data thus obtained is used to address a look up table which gives the code of the key
pressed.
LED display
165. The eight diodes D1-D8 provide ‘state’ information relating to the function switches.
Diodes D15-17 provide information on modulation frequency selected. This allows
unambiguous keyboard operation. ‘IC4 is an eight—bit data latch that drives the LEDs
through R10-R13 current limiting resistors. Only three resistors are required for the
eight LEDs because only one diode of D4-D8 will be lit at any one time. Data is placed
on the bus and then chip select CS4 is taken to logic ‘high’ momentarily. All IC4 outputs
are continuously enabled and thus any of the inputs, DO-D7 which were ‘high’ when CS4
went ‘high’ will give a logic ‘high’ output on QO-Q7. The nominal diode current taken by
a diode when operating is approximately 15 mA. Diodes D15-17 are controlled via IC3
and decoded by IC6. The coding is as follows:
46881-891U
Oct. 88 4-39
TECHNICAL DESCRIPTION
IC3 D15 D16 D17
D6 D7
0 0 OFF OFF OFF
0 1 ON OFF OFF
1 0 OFF ON ORE
1 1 OFF OFF ON
LCD display
166. IC1 and IC2 are the LCD controllers which accept complex strings of serial infor-
mation on pin 9 via the Serial Input (SI) line. They are able to store this and use it to
control which of the 128 display segments are turned on. Chip select lines CS1 and CS2
determine which IC is to receive data and the Command/Data (C/D) line determines the
way that the data is processed. i
167. Serial Clock Low (SCK L) line is clocked from A2/2 board via SKK pin 2. The
positive-going edge of SCK L cues the selected IC so that the serial input, $1 line can be
read. The display has two phases of backplane drive to enable two segments to be
connected with a single drive point. This halves the number of drive points required.
168. R& sets the internal clock frequency for both IC1 and IC2 and is divided by 211
which actually results in a backplane frequency of approx. 40 Hz for display driving. The
common connection between pin 2 of IC1 and IC2 ensures that both are synchronized.
Reset lines are coupled together and then connected via SKK, pin 18 to a latch on A2/2
board. At switch on and at any time the +5 V rail falls below a preset value the reset line
will be asserted logic ‘low’ and all data will be cleared from IC1 and IC2. It is necessary
to hold this line ‘low’ until the correct supply voltage is available to ensure synchro-
nization of the display backplane drives.
169. The display drive waveform is switched between three voltage levels provided by
TR1 and R1-R7. These are nominally (i) VLCD3 (+0.9 V) (ii) VDD (45 V) (iii) VLCDy
(+3 V), midway between VDD and VLCD3. The voltage on TR1 collector varies with
temperature to match changes that occur in the LCD fluid.
Two phase multiplexing
170. Liquid crystal displays are passive unlike LED active displays, which convert energy
into light. In the 2022E, multiplexed LCDs use a feature of the fluid in the device to
provide the display required. Changes in the polarization of light passing through it do
not occur until a certain RMS voltage is reached. Once this level has been exceeded the
segments to which the signal is being applied appear dark.
46881-891U
4-40 Oct. 88
TECHNICAL DESCRIPTION
BACKPLANE
ONE
BACKPLANE FE:
TWO
SEGMENT
BACKPLANE
ONE -
SEGMENT
TW
SEGMENT
Fig. 4-21 Typical waveforms, LCD drive waveforms (Al/2)
171. Fig. 4-21 shows typical waveforms generated at IC1 and IC2. There is a V5:1
difference in the RMS voltage between segment and backplane plates depending on
whether the segment is on or off. The backplanes remain as shown with a 180° phase
difference whilst the segment drive takes up one of four possible forms to produce the
four states required.
46881-891U
Oct. 88 4-41
TECHNICAL DESCRIPTION
40 dB STEP OUTPUT ATTENUATOR (AC0/A2/2)
Circuit diagram : Figs. 7-5 & 7-9
172. Instructions to operate the attenuator pads are initiated by means of the keyboard
and are then processed by the microprocessor via data lines DO-D4. A2/2 board IC22
receives a logic ‘low’ instruction to cause one (or more) of five control transistors
TR8-TR12 to turn on. This in turn completes the current path for one or more selected
relays on board AC1 via PLN pins 2-7. Relays RLA-RLE are normally de-energized
until the current path for the attenuator pad(s) relay is completed. When this occurs
current flows through the respective attenuator pad(s) relay and the contacts then make
to bring the pad(s) into circuit.
173. Diodes D17-D21 on A2/2 board act as clamps to protect the open collector drivers
TR8-TR12 from inductive spikes. When a relay is de-energized the stored magnetic
field causes a large negative-going voltage spike on the control line which is clamped by
the diodes. Adjustment to the attenuator pads are made by means of screws in the lid.
Frequency response is optimized by the adjustment of small flags which are moved by
these screws. Each pad is set up separately and requires the use of specialist measuring
facilities. It is therefore recommended that this is carried out by the nearest Marconi
Instruments Agent or Service Division.
174. Each attenuator pad consists of 3 precision resistors that provide attenuation
of 10 dB, 20 dB or 30 dB. Logic selection for each of the 10 dB steps from 0 to 120 dB is
shown in Table 4-4.
TABLE 4-4 ATTENUATOR LOGIC (ACO and A2/2)
dB
Attenuation 0 10 20 30 40 50 60 70 80 90 100 110 120
A 30 dB x X X X KX X KX KX X
Pads B 20 dB x xX Xx x x
circuit. C 30 dB xX X X X
D 10 dB x x Xx X X
E 30 dB xX X X X X X X
X = Relay energized
Reverse Power Protection (ACO and A2/2)
175. Resistors R16 and R17 form a high impedance RF signal divider at the output of the
attenuator which is used to sense the RF present at the output of the attenuator. Diodes
D1 and D2 peak detect the signal level onto C14 and C16. The resulting DC is connected
for use in the RPP system. If the signal level exceeds a preset limit relay RLF de-
energizes and sets the contacts to open circuit the output to SKAF, thus protecting the
attenuator from excessive power dissipation.
176. Decoupling capacitors C1-C12 and inductors L1-L8 reduce coupling of RF voltages
present inside the attenuator onto drive lines outside the box.
46881-891U
4-42 Oct. 88
PN
TECHNICAL DESCRIPTION
GPIB ADAPTER MODULE (ADO)
Circuit diagram : Fig. 7-10
177. This optional module, when fitted to the rear panel, allows direct connection to a
GPIB controller and provides full talker/listener facilities to IEEE 488 specifications.
178. GPIB talker/listener integrated circuit IC2, is connected to A2/2 board via SKP pro-
viding both talker and listener capabilities, details of these are given in Chapter 3 of the
Operating Manual. IC2 contains the gating registers and control circuit needed to inter-
face between the GPIB and the instrument’s 8-bit bus. Fig. 4-22 shows the basic
structure of the device. In its most elementary form data is entered into one of the
internal registers and then transferred to the GPIB or instrument bus depending on
whether a talk or listen mode is chosen. Further information on the general features and
applications of the GPIB system can be obtained from the separate GPIB manual (see Vol.
1, Optional accessories).
J
|
{
!
j
| :
|
| C 8 READ b=
| REGISTERS
| C_
|
8 WRITE Rd
TO BUS
GPIB CONTROL TRANS -
, CEIVERS
\
N
As TRANSMIT
——_,
N
A
L
: CONTROL
REGISTERS 3
MESSAGE
DECODER
Fig. 4-22 Internal structure of GPIB talker/listener integrated circuit, IC2 (ADO)
179. IC1, R1 and C8 operate as an independent clock whose frequency (between 1 and
2 MHz) is used to generate a delay of approximately 2 js allowing the bus to settle after
sending data. ICla is a Schmitt triggered input inverter with R1 and C8 providing
positive feedback to complete the oscillatory circuit. IC1b buffers the clock signal, which
is fed directly to IC2, GPIB chip.
180. Sixteen lines are buffered by IC3-IC6, these act as transceivers and are used to
translate the negative true logic and act as drivers. Data lines, DAV, NDAC, NRFD and
EOI lines have bi-directional buffers. The remaining lines with the exception of the SRO
line are receivers. JIC1e,f provides the logic ‘low’ level for the receive instruction T/R to
IC4 pins 7 and 9; or the talker ‘high’ level for IC4, IC5 and IC6 and also provides
additional buffering for the three ICs in line. IC2 pin 2 controls the mode of the EOI
line.
46881-891U .
Oct. 88 4-43
TECHNICAL DESCRIPTION
THIS PAGE INTENTIONALLY LEFT BLANK.
46881-891L
4-44 Oct. 88
SECOND FUNCTION OPERATIONS
181. Second function operations provide the means of controlling various secondary
features and calibrations within the instrument.
of which require unlocking in order to gain access.
of access is described below.
182. Normal operation
Second
functions
‘0’ Unlock
‘1’ Status information
‘2’ GPIB address setting
‘3’ Manual latch setting
‘4’ SRO mask setting
‘5’ Read identity string
‘6’ Front panel ‘Test display’
‘7’ Reserved for future use
‘8’ Reserved for future use
‘9’ Read elapsed time since
last reset
183. First level operation
Second
functions
‘10’ Record external freq. std.
choice
‘11’ Read identity string
‘12’? Write user—definable string
(GPIB only)
‘13’ Read user-definable string
(GPIB only)
‘14’ Set RF level! units setting
‘15’ Set RF level offsets
‘16’ Recall STORE 10 at switch-on
‘17’ Reserved for future use
‘18’ Reserved for future use
184. Second level operation
Second
functions
46881-891U
Oct. 88
‘190’ Set identity string
‘191’ FM tracking calibration
‘192’ RF level calibration
‘193’ Voltage tuned filter (VIF)
calibration
‘194’ AM calibration
‘195’ Calibration and storage of
amended EAROM checksum
‘196’ Protection of store settings
‘197’ Display blanking of
recalled stores
‘198’ Read total instrument
operating time
‘1990’ Reset of second function 9
elapsed time.
‘1991’ Reset non-volatile stores.
TECHNICAL DESCRIPTION
There are three levels of operation, two
Each level of operation and method
These functions are un-
protected and may be
accessed directly:-
Press 2ND FUNCT fol-
lowed by the numeral
required.
These functions have first
degree protection and are
accessed by the following
procedure:— Press 2ND
FUNCT 0, then the L (dec-
rement) and MOD ALC keys
simultaneously, holding both
these down until a ‘1’ appears
in the Frequency display.
Follow this by again pressing
2ND FUNCT, and the
numerals required.
These functions have second
degree protection and are
accessed by the following
procedure:- 2ND FUNC 0,
then in the following order
| (decrement), MOD ALC, 4
and kHz keys, holding down
all four until a ‘2’ appears in
the Frequency display.
Follow this by again pressing
2ND FUNCT and the
numerals required.
4-45
TECHNICAL DESCRIPTION
SECOND FUNCTION OPERATIONS (see SECURITY NOTICE on page ii)
181. Second function operations provide the
tures and calibrations within the instrument.
which require unlocking in order to gain access.
access is described below.
182. Normal operation
Second ‘Q’
functions
Unlock
Status information
GPIB address setting
Manual latch setting
SRO mask setting
Read identity string
Front panel ‘Test display’
Reserved for future use
Reserved for future use
Read elapsed time since
last reset
183. First level operation
Second *10’
functions
r | 1 b
$12"
*13°
*14’
ao oy
‘16’
‘17°
18°
Record external freq. std.
choice
Read identity string
Write user-definable string
(GPIB only)
Read user-definable string
(GPIB only)
Set RF level units setting
Set RF level offsets
Recall STORE 10 at switch-on
Reserved for future use
Reserved for future use
184. Second level operation
Second
functions
‘190’ Set identity string
‘191’ FM tracking calibration
‘192’ RF level calibration
‘193° Voltage tuned filter (VIF)
calibration
‘194’ AM calibration
‘195’ Calibration and storage of
amended EAROM checksum
‘196’ Protection of store settings
‘197’ Display blanking of
recalled stores
‘198’ Read total instrument
operating time
‘1990’ Reset of second function 9
elapsed time.
‘1991’ Reset non-volatile stores
46881-891U
Oct. 88
means of controlling various secondary fea-
There are three levels of operation, two of
Each level of operation and method of
These functions are un-
protected and may be
accessed directly:—
Press 2ND FUNCT fol-
lowed by the numeral
required.
These functions have first
degree protection and are
accessed by the following
procedure:— Press ZND
FUNCT 0, then the L (dec-
rement) and MOD ALC keys
simultaneously, holding both
these down until a ‘1’ appears
in the Frequency display.
Follow this by again pressing
2ND FUNCT, and the
numerals required.
These functions have second
degree protection and access
to Second level operation is
restricted to authorized cali-
bration units only. Inter—
ference with these second
functions could invalidate
the instrument’s calibration.
4-45a
merge
Poca
TECHNICAL DESCRIPTION
185. Second function ‘3’ Manual latch setting. Second functions that are used in normal
operation of the instrument are described in the Operating Manual Vol. 1. Second
function 3 Manual latch setting, however, is used only in maintenance applications and is
therefore described here. This facility allows the operator to direct a 6 or 8 bit binary
instruction to any of the instrument’s internal latches or registers for testing and fault
finding. The latch is accessed by first selecting 2ND FUNCT 3 mode then keying in the
address number, 00 to 35. Latch address numbers are identified in both Chap. 7,
Servicing diagrams and Chap. 5, Maintenance.
186. Selection of second function 3 results in the following display:—
|
The instrument now awaits entry of the latch number which will be displayed in the
carrier frequency window until selection is completed. When this occurs the display will
change to one of two formats depending on whether a 6-bit or an 8—bit latch has been
addressed.
187. 6—bit latches. When the address latch number has been entered the display will
change and the current value of data normally applied to the latch is presented in binary
notation as shown in the example below:-
XXXXKX
:
b ae
Where XXXXXX = binary data
YY = latch number
3 = second function selection
188. Data can now be entered in binary (6 digits 000000 to 111111), with data being
shifted in, most significant bit first. When data is satisfactorily set press the STORE key
to terminate the entry; the decimal points will flash briefly to indicate that the data has
been sent.
189. 8-bit latches. Selection of an 8-bit latch or register will result in an identical initial
display as that shown for a 6-bit latch selection. However, when address selection is
complete data is displayed not in binary but decimal notation in the following manner:-
Where ZZZ = present decimal data
—-— = new data entry point
YY = latch number
3 = second function selection
46881-891U
Oct. 88
4-46
TECHNICAL DESCRIPTION
185. Second function ‘3’ Manual latch setting. Second functions that are used in normal
operation of the instrument are described in the Operating Manual Vol. 1. Second
function 3 Manual latch setting, however, is used only in maintenance applications and is
therefore described here. This facility allows the operator to direct a 6 or 8 bit binary
instruction to any of the instrument’s internal latches or registers for testing and fault
finding. The latch is accessed by first selecting 2ND FUNCT 3 mode then keying in the
address number, 00 to 35. Latch address numbers are identified in both Chap. 7,
Servicing diagrams and Chap. 5, Maintenance.
186. Selection of second function 3 results in the following display:—
The instrument now awaits entry of the latch number which will be displayed in the
carrier frequency window until selection is completed. When this occurs the display will
change to one of two formats depending on whether a 6-bit or an 8-bit latch has been
addressed.
187. 6-bit latches. When the address latch number has been entered the display will
change and the current value of data normally applied to the latch is presented in binary
notation as shown in the example below:—
Where XXXXXX
= binary data
YY = latch number
3 second function selection
188. Data can now be entered in binary (6 digits 000000 to 111111), with data being
shifted in, most significant bit first. When data is satisfactorily set press the STORE key
to terminate the entry; the decimal points will flash briefly to indicate that the data has
been sent.
189. 8-bit latches. Selection of an 8-bit latch or register will result in an identical initial
display as that shown for a 6-bit latch selection. However, when address selection is
complete data is displayed not in binary but decimal notation in the following manner:-
Where ZZZ = present decimal data
new data entry point
YY = latch number
3 = second function selection
46881-891U
Oct. 88
4-46a
))
TECHNICAL DESCRIPTION
Decimal data entered will shift in most significant digit first. On completion press
STORE key, when the data on the right of the display will be sent to the latch. This is
indicated by the instrument copying the new entered data into the left side of the
frequency window and replacing the right side with “ -—- ”. ready for a further entry.
190. Any new data sent to a 6-bit or 8-bit latch will remain valid until the manual latch
addressing mode is terminated by pressing one of the mainfunction keys. At this time
the latch data will be restored to its normal status.
191. Second function ‘190’ Set identity string. This facility is second degree protected
and is only normally required to initialize the instrument. The identity string shows the
instrument type number and serial number. This information can be read via the GPIB.
A typical display is described in the Operating Manual Vol. 1, Second function 5, Read
identity string. Instrument type number and software issue number is shown first e.g.
52022-930, then the software issue number e.g. 004. This cannot be changed via the
keyboard as it is built into the software. Pressing the ‘.’ decimal point key then allows
the second half of the string containing the serial number of the instrument to be entered.
192. Entering digits first clears the display and then rotates the numbers in from the
right-hand side of the frequency display. When setting the first half of the string the
most significant digit will be entered but will rotate off the end of the display. Press
STORE to terminate this entry. Press ‘.’ (decimal point) to display the second part of the
string and key in the nine digits required to enter the serial number, in this event the two
most significant digits will not be displayed. Again press the STORE key to terminate the
entry. In each case pressing the STORE key will show the new data in the normal display
format.
193. Second function ‘191’ FM tracking calibration. The FM tracking calibration data
consists of two tables of calibration points. The first, which covers the frequency range
250.0000 MHz to 352.9999 MHz, has 25 calibration points spaced 4.12 MHz apart, with
the exception of point 24 which is 100 Hz less than 4.12 MHz (4.1199 MHz) to avoid
overlapping with the higher table. The second table covers frequencies from 353.0000
MHz to 499.9999 MHz and also has 25 points, each 5.88 MHz apart except for the 25th
point. This is again 100 Hz less (5.8799 MHz), to avoid overlapping with point 24.
Details of the calibration procedure are given in Chap. 5 Maintenance.
194. Second function ‘192’ RF level calibration. The output level is calibrated at 11
selected reference points, each point is numbered from 00 to 10 with the selected point
displayed in the modulation window. Point 00 is at 15 MHz and points 01 to 10 are
spaced at intervals of 100 MHz, starting at 100 MHz and finishing at 1010 MHz. Existing
calibration data is shown on the left side of the frequency window in decimal form, new
data when it is entered is displayed on the right. Pressing the STORE key transfers the
new data to the non-volatile (EAROM) memory.
195. Second function ‘193’ Voltage tuned filters (VIF) calibration. The voltage tuned
filter (VIF or Output harmonic control) calibration table consists of 6 points running
from 500 MHz to 1010 MHz in 100 MHz steps. Display and calibration procedures are
identical to those described in the FM tracking and RF level calibration paragraphs.
196. Second function ‘194’ AM calibration. Only two calibration points exist for AM.
Point 00 is calibrated at 15 MHz and point 01 is calibrated at 100 MHz. Calibration is as
described in previous paragraphs with the user entering decimal data on the right side of
the frequency window then pressing the STORE key to save the new data in the EAROM.
46881-891U
Oct. 88 4-47
TECHNICAL DESCRIPTION
197. Second function ‘195’ Calculation and storage of amended EAROM checksum. A
check on the serviceability of both PROM and RAM is carried out before the instrument's
initial operating mode is displayed and a checksum is initiated on the EAROM stored
data. If either PROM or RAM checks are in error the instrument will be unable to take
up the initial operating mode and instead will display an error message, either 06 or 08,
depending on the fault. Error messages are described in the Operating Manual Vol. 1. If
4 new non-volatile EAROM has been fitted or if new RF level calibration or FM tracking
data has been entered (as a result of recalibration) the checksum will not agree and Error
number 07 will be displayed in the carrier frequency window until a key is pressed. To
recalculate the EAROM checksum enter 2ND FUNC 195 (which will display the current
checksum) and press the STORE key. The instrument will re-calculate the checksum,
store it in EAROM and display 000 to indicate the completion of the task.
198. Second function ‘196’ Protection of store settings. This facility disables the
operation of the STORE key in the normal mode of operation in order to provide
protection against inadvertent alteration. On selecting second function 196 the frequency
window gives a display of either ‘0’,*1’,‘2’ or ‘3°. These numbers indicate the following:—
0 = stores unlocked, offsets unlocked
1 = stores locked, offsets unlocked
2 = stores unlocked, offsets locked
3 = stores locked, offsets locked
Attempts to overwrite the store contents when protected will result in Error message 18
being displayed in the carrier frequency window.
199. Second function ‘197’ Display blanking of recalled stores. This facility enables
restrictions to be exercised on the display of data set in stores should this be of a
classified nature. Front panel display information is blanked when any store (other than
00) is recalled. All information concerning the existing status, with the exception of
error messages and total shift data is prevented from reaching the display. Select ‘1’
followed by the STORE key to enable the facility. To disable the facility and return the
‘nstrument to the normal display mode press ‘0’ and STORE keys. Recall of store 00 will
always give a valid display of that stores contents regardless of the state of second
function ‘197’ and will also return the instrument to the normal display mode.
200. Second function ‘198’ Read total instrument operating time. This read only
facility gives the total number of operating hours since instrument manufacture. Selection
of this second function will display the record of elapsed time (in hours), in the carrier
frequency window with a resolution of 0.5 hrs. When first receiving the instrument a
display of time will be evident, reflecting the time spent during manufacture.
Note ...
There is no facility for resetting the total instrument operating time.
201. Second function ‘1990’ Reset second function 9 elapsed time. This elapsed time
facility can be reset to zero by means of this second function control. When wishing to
reset, first select second function ‘1990’ then press the ‘STORE’ key.
202. Second function ‘1991’ Reset non-volatile stores. This function permits all of the
instrument’s 100 stores to be reset to their default settings. To operate, select second
function ‘1991’ then press the ‘STORE’ key. Note that it will take the instrument about 40
seconds to do this.
46881-891U
4-48 Oct. 88
Pei
| Chapter 5-0
MAINTENANCE
CONTENTS
1 Introduction
3 Safety precautions
4 Handling precautions
7 Recommended test equipment
8 Access and removal of boards
9 AA1/1 and AA2/1 boards
11 AB1/2 board and removal of ABO unit
13. A2/2 board
16 A1/2 keyboard
17. Rear panel mounting of RF OUTPUT socket
Table Page
5-1 Recommended test equipment 2
5-2 Decibel conversion table 4
Fig.
7
5-1 Access and layout
INTRODUCTION
1 This chapter provides servicing support information for the three chapters which
i.
follow :
5-1 : PERFORMANCE TESTING - procedures for verifying that the equipment
complies with the Performance Data in Chap. 1.
5-2 : ADJUSTMENT AND CALIBRATION - tests and adjustments for restoring
' the equipment to peak performance.
5-3 : FAULT DIAGNOSIS - procedures for localizing faults, first to sub-assembly
level (normally a printed circuit board), and then to component level.
2 In case of difficulties which cannot be resolved with the aid of this manual, please
contact our Service Division at the address at the rear of the manual or your nearest
Marconi Instruments representative. Always quote the type number and serial number
found on the instrument data plate.
SAFETY PRECAUTIONS
3. Although this equipment has been designed and constructed in accordance with
international safety standards, it is important that the advice given under SERVICING
PRECAUTIONS at the front of this manual should be observed in all maintenance
procedures to ensure safe working practices.
46881-891U ;
Oct. 88 5-1
MAINTENANCE
HANDLING PRECAUTIONS
4. Integrated circuits and semiconductor devices are used throughout this instrument
and, although these have inherent long term reliability and mechanical ruggedness, they
are susceptible to damage by overloading, reverse polarity and excessive heat or radiation
and the use of insulation testers.
5. Static sensitive components. The CMOS integrated circuits used in this instrument
have extremely high input resistance and can be damaged by accumulation of static
charges (see page iii - SERVICING PRECAUTIONS). Boards that have such integrated
circuits all carry warning notices against damage by static discharge. Care must also be
taken when using freezer sprays to aid fault finding. These can create a static charge
likely to change the programmed memory of (E)PROMS.
6. Bulkhead connectors and gaskets. Special care should be taken to ensure that no
RF leakage occurs. To this end all bulkhead connectors and lid sealing gaskets should be
secure. It is essential that the unit lids be correctly relocated in their slotted recesses
after removal. | When disconnecting an RF connection between units ensure that the
metal clad connectors do not accidentally cause short circuits on adjacent PCBs.
Whenever possible ribbon cable connectors are polarized but care should still be taken to
ensure that these are not misplaced. The printed board legends also have a cross
hatching printed to indicate the direction by which any given ribbon cable should leave
that board.
RECOMMENDED TEST EQUIPMENT
7. The test equipment recommended for use in Chaps. 5-1, 5-2 and 5-3 is shown in
Table 5-1. Alternative equipment may be used provided it complies with the stated
measurement requirements.
TABLE 5-1 RECOMMENDED TEST EQUIPMENT
Item Description Measurement requirements Recommended model* |
a Modulation meter Range ®M:0.01 to 9.99 radians 2305 & Distortion
with distortion FM: 10 Hz to 99.9 kHz options kit (or
measuring facility AM: 0 to 99.5% TF 2331A)
Accuracy FM & ®M: +5% of devia-
tion at 1 kHz
AM: +4% of depth
setting +1%
Distortion
AM, FM & ©M: <5% total har-
monic distortion
b Frequency counter Freq. range: 10 kHz to 1 GHz. 2435
Accuracy: Better than +2
in 107 over the
temperature range
0 to 40°C
* Marconi Instruments type unless otherwise indicated
46881-891U
Oct. 88
as
TABLE 5-1
Item Description
Cc
Standard frequency
source (1,5 or
10
MHz)
RF Power Meter
with Power Sensor
AC Voltmeter
AF Signal Source
RF Millivoltmeter
T Connector
N type 50 Q load
Short circuit
monitor
20 cm Air spaced
line
20 cm Adjustable
line
DC microvoltmeter
Spectrum analyzer
Variable DC power
supply
Distortion factor
meter
Signal generator
(low noise)
RF Mixer
Low-pass filter
46881-891U
Oct. 88
MAINTENANCE
RECOMMENDED TEST EQUIPMENT (continued)
Measurement requirements
Output level: >1 V RMS
Output level: -127 dBm to +6 dBm
Level accuracy: +1 dB from 10 kHz
to 1 GHz
Output level: 1 V +10% EMF
Frequency range: 50 Hz — 25 kHz .
Output level: 0.90-1.10 V
VSWR: <1.5:1
Freq. range: 10 kHz-350 MHz
VSWR: <1.5:1
Freq. range: 10 kHz-350 MHz
VSWR: <1.5:1
Freq. range: 10 kHz-350 MHz
VSWR: <1.5:1
Freq. range: 350-1000 MHz
VSWR: <1.5:1
Freq. range: 350-1000 MHz
VSWR: <1.5:1
Freq. range: 350-1000 MHz
Voltage range : >3 wV FSD
Freq. range: 15 MHz-1.5 GHz
Voltage: +5 V
Distortion AM,FM & ®M: <5% total
Distortion MOD OSC: <1% total
Frequency range: 10 kHz-1024 MHz
RF level: >0 dBm
Residual FM: typically less
than 1 Hz up to 512 MHz,
2 Hz up to 1024 MHz
-1-1000 MHz
2 MHz LPF
Recommended model
Rubidium or
Caesium reference
unit
6960 & 6912
2610
Any suitable model |
TF 2603
T{ 7984
TM 7967
GR 874-L20
GR 874-LK20L
LEVELL Type TM8
TF 2158
TF 2331A
TE 2017
Mini—circuits ZRFM-2
MAINTENANCE |
TABLE 5-2 DECIBEL CONVERSION TABLE
Ratio down Ratio up
Voltage Power Decibels Voltage Power
1.0 1.0 0 1.0 1.0
9886 .9772 1 1.012 1.023
9772 9550 ) 1.023 1.047
.9661 .9333 3 1.035 1.072
9550 9120 4 1.047 1.096
9441 8913 5 1.059 1.122
.9333 ~ .8710 6 1.072 1.148
9226 8511 7 1.084 1,175
9120 8318 8 1.096 1.202
9016 8128 9 1.109 1.230 cs
8913 .7943 1.0 £3122 1.259
.8710 .7586 1.2 1.148 1.318
8511 7244 1.4 1.175 1.380
.8318 .6918 1.6 1.202 1.445
.8128 .6607 1.8 1.230 1.514
.7943 .6310 2.0 1.259 1.585
.7762 .6026 2.2 1.288 1.660
.7586 5754 2.4 1.318 1.738
.7413 5495 2.6 1.349 1.820
7244 5248 2.8 1.380 1.905
.7079 5012 3.0 1.413 1.995
.6683 4467 3.5 1.496 2.239
.6310 3984 4.0 1.585 2.512
5957 3548 4.5 1.679 2.818
5623 3162 5.0 1.778 3.162
.5309 .2818 5.5 1.884 3.548 -
5012 2512 6 1.995 3.981 eo
4467 .1995 7a 2.239 5.012
3981 1585 8 2.512 6.310
3548 1259 9 2.818 7.943
.3162 .1000 10 3.162 10.000
.2818 07943 slp 3.548 12.59
.2512 .06310 12 3.981 15.85
.2239 .05012 13 4.467 19.95
.1995 03981 14 5.012 25.12
.1778 .03162 15 5.623 31.62
46881-891U
Oct. 88
Ratio down
Voltage Power
1585 02512
1413 .01995
.1259 01585
1122 01259
.1000 .01000
.07943 6.310 x 10-3
.06310 3.981 x 10-3
05012 2.512 x 10-3
03981 1.585 x 10-3
03162 1.000 x 10-3
02512 6.310 x 10-4
.01995 3.981 x 10-4
01585 2.512 x 10-4
.01259 1.585 x 10-4
.01000 1.000 x 10-4
7.943 x 10-3 6.310 x 10-5
6.310 x 10-8 3.981 x 10-5
5.012 x 10-3 2.512 x 10-5
3.981 x 10-3 1.585 x 10-5
3.162 x 10-3 1.000 x 10-5
2.512 x 10-3 6.310 x 10-6
1.995 x 10-3 3.981 x 10-6
1.585 x 10-3 2.512 x 10-6
1.259 x 10-3 1.585 x 10-6
1.000 x 10-3 1.000 x 10-6
5.623 x 10-4 3.162 x 10-7
3.162 x 10-4 1.000 x 10-7
1.778 x 10-4 3.162 x 10-8
1.000 x 10-4 1.000 x 10-8
5.623 x 10-5 3.162 x 10-9
3.162 x 10-5 1.000 x 10-9
1.000 x 10-5 1.000 x 10-10
3.162 x 10-6 1.000 x 10-11
1.000 x 10-6 1.000 x 10-12
3.162 x 10-7 1.000 x 10-13
1.000 x 10-? 1.000 x 10-14
46881-891U
Oct. 88
Decibels
16
17
18
19
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
MAINTENANCE
TABLE 5-2 DECIBEL CONVERSION TABLE (continued)
Ratio up
Voltage Power
6.310 39.81
7.079 50.12
7.943 63.10
8.913 79.43
10.000 100.00
12.59 158.5
15.85 251.2
19.95 398.1
25:19 631.0
31.62 1000
39.81 1.585 x 108
50.12 2.512 x 108
63.10 3.981 x 105
79.43 6.310 x 10
100.00 1.000 x 104
125.9 1.585 x 104
158.5 2.512 x 104
199.5 3.981 x 104
251.2 6.310 x 104
316.2 1.000 x 105
398.1 1.585 x 105
501.2 2.512 x 105
631.0 3.981 x 108
794.3 6.310 x 105
1000 1.000 x 104
1.778 x 108 3.162 x 104
3.162 x 103 1.000 x 107
5.623 x 108 3.162 x 107
1.000 x 104 1.000 x 108
1.778 x 104 3.162 x 108
3.162 x 104 1.000 x 109
1.000 x 105 1.000 x 1010
3.162 x 105 1.000 x 1011
1.000 x 106 1.000 x 1012
3.162 x 106 1.000 x 1013
1.000 x 107 1.000 x 1014
MAINTENANCE
ACCESS AND REMOVAL OF BOARDS
8. Access to the interior of the instrument can be gained by first removing the rear -
casting which is retained by two centre fixing cross headed screws. Both top and bottom
outer covers can then be removed.
Access to AA1/1 and AA2/1 boards
9. Remove eight of the screws that secure AAO cover plate. There are five screws on
either side of the unit but the two centrally mounted ones should not be removed because
they secure AAO unit to the side-frames (see Fig. 5—1a for details). AAO cover plate can
now be raised to access board AA2/1 which is attached to the underside of AAO cover
plate. Board AA1/1 is situated inside AAO unit.
10. If it is required to remove AA2/1 then connectors PLAA, PLAB and PLAC should
be detached from the board. Alternatively the cover plate can be rotated through 180° —
and secured with two screws into the servicing position as shown in Fig. 51a.
Access to AB1/2 board and removal of ABO unit
11. Place the instrument upside down and remove the eight outermost fixing screws
(shown in Fig. 5-1a). Remove the cover plate which will give access to board AB1/2.
12. The two remaining centrally mounted fixing screws secure ABO unit to the side
frames. To remove ABO, unscrew the two remaining centrally mounted fixing screws and
conhex connectors SKW and SKZ. Raise ABO unit at the rear of the instrument, pivoting
about the front edge until it is possible to remove sockets SKN and SKM from A2/2
board. Finally remove the RF output connector, PLAF, from the attenuator and
withdraw ABO unit. When replacing ABO unit, ensure that the GPIB module ADO is
correctly located between the two guides on the underside of ABO. If difficulty is
experienced, remove ADO (see para. 14) before attempting to replace ABO.
Access and removal of A2/2, Power supply and Control board
13. Access to this board is achieved by removing ABO unit as described in the previous
paragraph. To remove A2/2 PCB, disconnect the sockets from the following plugs, PLF,
PLH, PLAG, PLJ, PLL and PLK, then disconnect SKP from the GPIB module ADO. The
board can then be released from the instrument after removing the nine fixing screws.
14. Before access can be gained to the components on the rear panel, GPIB module
ADO (if fitted) must be withdrawn from the instrument. Remove the two cross—headed
screws securing the module to the rear panel. Carefully slide out the board assembly
from the instrument as shown in Fig. 5-1b. Also withdraw the inter-connecting lead and
disconnect SKP socket from the GPIB module. :
15. Remove the two upper screws that secure the rear panel to the side frame and
loosen only the two lower securing screws as shown in Fig. S-id. The rear panel can
now be partially hinged to allow access to SKR, STD FREQ IN socket. Detach this and
the rear panel is then free to angle down.
Note ...
When replacing GPIB module ADO, attach the interconnecting lead and socket SKP
to the rear of the board. Then slide the unit into the instrument ensuring that the
component side of board AD1 is facing the side frame of the instrument. Also
check that the board locates correctly between the guides shown in Fig. 5-1b.
46881-891U
Oct. 88
MAINTENANCE
Access and removal of A1/2 keyboard
16. Limited access to the keyboard can be obtained without removing either AAO or
ABO units. First ensure that the AC supply is disconnected from the instrument. Now
remove the two outer instrument covers and then the four screws (two in each side frame)
securing the front panel to the side frame. Turn the instrument upside down and remove
the nut securing the SUPPLY ON-OFF switch. Push the switch back through the front
panel. Disconnect the MOD IN-OUT socket SKJ from A2/2 board. It is now possible to |
hinge the front panel about the side of the RF OUTPUT socket. Access can now be
gained to the rear of A1/2 keyboard which can be removed after withdrawing six cross-
headed securing screws.
Rear panel mounting of RF OUTPUT socket
17. General instructions for rack mounting are given in Chap. 2 of the Operating
Manual. The RF OUTPUT socket can be mounted on the rear panel without recourse to
additional wiring. A front panel blanking grommet is supplied to insert in the vacated
position if required.
18. First remove RF unit ABO as described in previous paragraphs. Now remove the
four cross-headed screws securing the front panel to the side frames and disconnect
socket SKK from A2/2 board. The front panel can now be hinged to allow access.
Keyboard A1 can now be removed from the front panel support by removing the six
cross-headed screws. Access to the RF OUTPUT 'socket is now possible. Unfasten the
retaining nut holding the socket to the front panel and refit the socket to the rear panel
position after removing and discarding the blind grommet. Re-assemble the front panel
unit and refit ABO.
46881-891U
Oct. 88 5-9
5-10
THIS PAGE INTENTIONALLY LEFT BLANK.
MAINTENANCE
46881-891U
Oct . 88
a,
j
Chapter 5-1
PERFORMANCE TESTING
CONTENTS
Para.
1 Introduction
3 Test precautions
4 Performance tests
4 Frequency accuracy
3 RF output
fi Modulation oscillator performance
8 FM deviation and distortion
9 Phase modulation and distortion
10 AM depth and distortion (Internal)
12 External modulation (ALC on)
13. External modulation (ALC off)
14 Auxiliary modulation
15 VSWR (50 kHz - 350 MHz)
16 VSWR (above 350 MHz)
17. Carrier harmonics and sub-harmonics
18 Residual FM
19 Reverse power protection
Table
5-3 ACO0/AC1 attenuator check
fz
=
Test gear arrangements :
Frequency accuracy
RF output
Mod. osc. performance
FM deviation and distortion
Phase mod. and distortion
AM depth and distortion
External modulation
Auxiliary modulation
-10 VSWR up to 350 MHz
-11 VSWR above 350 MHz
-~12 Carrier harmonics and sub-harmonics
-13 Residual FM =
1 ot tod
mW dN
|
eee aaa aa aieceys
ain PAA AAA AA Nn
46881-891U
Oct. 88
Page
5-11
PERFORMANCE TESTING ~
INTRODUCTION
1. The test procedures in this chapter enable you to verify that the electrical perform-
ance of the Signal Generator complies with the Performance Data given in Chap. 1 (in the
Operating Manual). The test equipment recommended for this purpose is listed in Chap.
50. All tests may be performed with the covers in place and are intended to be carried
out in the order given. For convenience, the test equipment and specification for each
test are summarized before the test procedure.
2. If the test results are outside limits, refer to the related part of the adjustment and
calibration procedure (Chap. 5-2).
TEST PRECAUTIONS
3. To ensure minimum errors and uncertainties when making measurements, it is im-
portant to observe the following precautions:—
(1) Always use recently calibrated test equipment, with any correction figures
taken into account, so as to establish a known or traceable limit of perfor—
mance uncertainty. This uncertainty must be allowed for in determining the
accuracy of measurements.
(2) A common external frequency standard, with an accuracy within +1 part in .
108, should be used for the generator and other frequency controlled test
equiupment. |
(3) Use the shortest possible connecting leads; ideally the generator should be
directly coupled to the test equipment.
(4) Allow a warm-up time of half an hour before commencing tests.
46881-891U
5-12 Oct. 88
4
PERFORMANCE TESTING
—~ PERFORMANCE TESTS -
Frequency accuracy
TEST EQUIPMENT 2022E PERFORMANCE DATA
(a) Frequency Counter 2435 Freq. range: 10 kHz to 1.01 GHz.
Accuracy: Equal to freq. std.
2022€
SIGNAL GENERATOR
2435
FREQUENCY COUNTER
6) cooaanO
TPB S19t
Fig. 5-2 Test gear arrangement to check frequency accuracy
LL tbebete Le
Lu LLLLE LL
“©
@Lt LLLL b&b
Lu bebe ek
Procedure
(1) Connect test equipment as shown in Fig. 5-2 and set the 2022E controls
as follows :
CARR FREQ : 10 kHz
AM : OFF
FM/®M : OFF
RE LEVEL : -10 dB
(2) Carry out spot checks throughout the range of the instrument ensuring that
frequencies can be selected correctly and that they are within specification.
(3) If you are using an external frequency standard, connect this to the rear panel
STD FREQ IN socket. One of three frequencies can be used (1, 5 or 10 MHz)
provided that an internal link selection within the 2022E corresponds to the fre-
quency of the external standard. The link setting can be determined by selecting
Second function 1 ‘Status’ mode, which will display 1, 5 or 10 in the Modulation
window.Instructions on changing the link setting are given in Chap. 5-2, para. 11.
(4) The level of an external frequency standard should be greater than 1 V RMS.
46881-891U .
Oct. 88 5-13
PERFORMANCE TESTING
RF output
a: TEST EQUIPMENT 2022E PERFORMANCE DATA
(d) RF Power Meter 6960 Level: —127 dBm to +10 dBm
and Power Sensor 6912 Level accuracy: Better than >1 dB
from 10 kHz-1.01 GHz
(-10 dBm to +6 dBm)
1 dB from 10 kHz-1.01 GHz
(above -10 dBm).
>2 dB from 10 kHz—-1.01 GHz
(below -10 dBm).
2022€
SIGNAL GENERATOR
6960
POWER METER om
Le ELee Le :
LL belt Lb cage el
OEE ELLE LEQ]
6912
POWER
SENSOR
Fig. 5-3 Test gear arrangement to check RF output
Procedure
(1) Connect test equipment as shown in Fig. 5-3 and set the 2022E controls as
follows :
CARR FREQ: 500 MHz “4
AM : OFF =
FM/®M : OFF
RF LEVEL : -10 dBm (70.7 mV PD)
(2) Note the power reading at -10 dBm and check that this is within specification.
Maintain this level setting and select other carrier frequencies e.g. 100 kHz, 1 MHz,
100 MHz and 1000 MHz.
(3) Further check other level settings up to a maximum of +10 dBm (0.707 V PD).
(4) Set the RF output level to 0 dBm. Check on the power meter that the 2022E
output remains flat to within +1 dB from 30 kHz to 1010 MHz.
46881—-891U
Oct. 88
PERFORMANCE TESTING
6. The 10 dB step attenuator ACO contains three 30 dB pads, one 20 dB pad and one
10 dB pad. Each of these may be selected individually by utilizing the Second function 3
mode. Levels below -10 dBm can best be checked by this method as follows:—
(1) Set the 2022E RF OUTPUT to +10 dBm and set a reference level of 0 dB on
the Power Meter 6960. ACO, step attenuator is controlled from A2/2 board address
05. To select each relay in turn enter by means of the keyboard controls Second
function 3, then 05. If unfamiliar with this procedure see ‘Manual latch setting’ in
Chap. 5-3, para. 62.
(2) The data showing in the Frequency window is that which is currently addressed
to the attenuator latch in binary notation. Enter new data by means of ‘1’ or ‘0’
numerals via the instrument keyboard. Numbers are rotated in from the right.
When the data is set press the STORE key and the appropriate relay will energize.
See Table 5-3 for each attenuator relay selection.
TABLE 5-3 ACO/AC1 ATTENUATOR CHECK
Binary number Relay Attenuation
D5 D4 D3 D2 OD1_ ODO energized
0 1 1 1 1 0 RLA 30 dB
0 1 1 1 0 1 RLB 20 dB
0 1 1 0 1 1 RLC 30 dB
0 1 0 1 1 1 RLD 10 dB
0 0 1 1 1 1 RLE 30 dB
(3) Check that the output falls to the appropriate level on the power meter as each
attenuator pad is selected. Typical accuracy expected is as follows: 10 dB +0.2 dB,
20 dB +£0.25 dB and 30 dB +0.3 dB.
(4) A spectrum analyzer may be used as an alternative to check levels down to -90
dBm with limited accuracy.
46881-891U
Oct. 88 5-15
PERFORMANCE TESTING
Modulation oscillator performance
a: TEST EQUIPMENT 2022E PERFORMANCE DATA
(b) Frequency Counter 2435 Freq.: 400 Hz, 1 kHz, 5 kHz.
(e) True RMS Voltmeter 2610 Accuracy: +5%.
(p) Distortion Factor Meter Distortion: <1% total harmonic
TF 2331A distortion
Output level: 1 V +10% EMF from a nomi-—
nal 600 2 source impedance.
2435
FREQUENCY COUNTER
|} @ aqoocao
2022€
SIGNAL GENERATOR
2610
TRUE RMS YOLTMETER
! | Co
| , CL Beer oe
} FLLELELLEL Po Lk Lhe te
LLLLLLLL@® lami L. LLLL LL ©} |
| Moc cree +r QO]
TF 2331A
DISTORTION FACTOR METER
TPB 519 3B
Fig. 5-4 Test gear arrangement to check Mod. osc. performance
Procedure
(1) Connect test equipment as shown in Fig. 5-4 and set the 2022E controls as
follows:—
FM/®M : FM (INTERNAL)
MOD ON/OFF : ON
(2) Check that the frequency of the MOD IN/OUT signal is within specification.
(3) Remove the frequency counter and connect the voltmeter to the 2022E MOD
IN/OUT socket and check that the output level is within specification.
(4) Remove the voltmeter and connect the distortion factor meter and check that
distortion is within specification.
(5) Press MOD ALC button to select the next modulation frequency and repeat
tests for all three frequencies.
46881-891U
5-16 Oct. 88
PERFORMANCE TESTING
FM deviation and distortion
8. TEST EQUIPMENT 2022E PERFORMANCE DATA
(a)Modulation Meter 2305 Range: 10 Hz to 125 kHz for
with Distortion options kit carriers from 10 kHz to
125 MHz.
10 Hz to 250 kHz for
carriers from 125 MHz
to 250 MHz.
10 Hz to 500 kHz for
carriers from 250 MHz
to 500 MHz.
me 10 Hz to 999 kHz for
aa carriers from 500 MHz
to 1.01 GHz.
Deviation accuracy: >5% of deviation at
1 kHz mod. freq.
excluding residual FM.
Distortion: <3% total harmonic
distortion at 1 kHz
mod. freq. and max.
deviation for any carr.
freq. above 250 kHz.
2022€
SIGNAL GENERATOR
2305
MOOGULATION METER
Le eee Oe
bie LLL LL
Lt ebheb cb
@cc LLLL EL ®
ewe
TPS Sis8
Fig. 5-5 Test gear arrangement to check FM deviation and distortion
Procedure
(1) Connect test equipment as shown in Fig. 5-5 and set the 2022E controls as
follows:-
CARR FREQ: 250 MHz
FM/®M : FM
Deviation : 250 kHz
RF LEVEL : 0 dBm
(2) On the modulation meter select FM, 300 Hz - 3.4 kHz filter, noise averaging.
(3) Check on the modulation meter that the deviation indicated is within +5% of
that set. .
46881-—891U
Oct. 88 5-17
PERFORMANCE TESTING SB
(4) Repeat for random carrier frequencies from 500 kHz to 1010 MHz.
Note...
Measurement at 250 MHz with 250 kHz deviation is equivalent to measure-
ments at 500 MHz with 500 kHz deviation and 1 GHz with 1 MHz deviation
due to the operation of the instrument.
(5) Repeat for random deviation settings from 1 kHz to 250 kHz.
Note ...
For lower deviation settings the residual FM of the 2022E and 2305 will have
to be taken into consideration.
(6) Set the 2022E controls as follows :
CARR FREQ : 400 MHz _O'
FM/®M : FM
Deviation : 99.9 kHz
RF LEVEL : 0 dBm
(7) On the 2305 select “ DISTORTION” and check the distortion indicated is less
than 2%.
(8) Repeat with random carrier frequencies between 500 kHz and 1010 MHz.
46881-8391U
Oct. 88
PERFORMANCE TESTING
Phase modulation and distortion
9. TEST EQUIPMENT 2022E PERFORMANCE DATA
(a) Modulation Meter 2305 Range: 0.01 to 9.99 radians.
with Distortion options Deviation accuracy: >5% of deviation at
kit. 1 kHz mod. freq.
2022€
SIGNAL GENERATOR
a a
tL bette ou
Lo Leek ot
Orc Lebo eu @
excluding residual
phase mod.
Distortion: <5% total harmonic
distortion at 1 kHz
mod. freq and max.
dev. at any carrier
freq. above 250 kHz.
2305
MODULATION METER
TPH S166
Fig. 5-6 Test gear arrangement for checking phase mod. and distortion
Procedure
(1) Connect test equipment as shown in Fig. 5-6 and set the 2022E controls as
follows :
4
H
?
CARR FREQ: 250 MHz
FM/®M : ODM
Deviation : 9.99 Radians
RF LEVEL : 0 dBm
Because ®M and FM mostly share common circuitry it is necessary to check only
one deviation setting.
(2) On the 2305 ®M function key and check that the deviation reading is within
specification.
(3) Select 2305 DIST function key and check that the distortion is within specifica-
tion.
46881-891U
Oct. 88
5-19
PERFORMANCE TESTING
AM depth and distortion (Internal)
10. TEST EQUIPMENT 2022E PERFORMANCE DATA
(a)Modulation Meter 2305 Range: 0 to 99.5%.
with Distortion options Accuracy: >4% of depth setting +1% for
kit. 1 kHz mod. freq. and depths
up to 95% for carrier freas.
up to 62.5 MHz (80% for
carrier freqs. up to 400 MHz).
Freq. response: +3 dB from 20 Hz — 50 kHz.
Distortion: <3% total harmonic distortion
at 1 kHz modulation frequency
for depths up to 80% for car-—
rier frequencies up to 400 MHz.
<5% total harmonic distortion
at 1 kHz modulation frequency
for depths up to 95% for car-
rier frequencies up to 62.5 MHz.
2022€ !
SIGNAL GENERATOR —
MODULATION METER
eee ce |
JOEE EEE LE @ |
TPB S188
Fig. 5-7 Test gear arrangement to check AM depth and distortion
Procedure
5-20
(1) Connect test equipment as shown in Fig. 5-7 and set the 2022E controls as
follows :
Modulation : 95%
RF LEVEL : 0 dBm
A fixed frequency modulator is used to provide the modulation at carrier frequen-
cies below 62.5 MHz and envelope feedback is used for carrier frequencies above
62.5 MHz.
(2) On the 2305 select the 30 Hz to 50 kHz filter and AM function key. Check
that the displayed reading is within specification.
(3) Select 2305, DIST function key and check that the distortion is within specifi-
cation.
46881-891U
Oct. 88
PERFORMANCE TESTING
(4) Reset 2022E controls :
CARR FREQ: 200 MHz
AM . :
Modulation : 80%
RF LEVEL : 0 dBm
11. Again check the depth and distortion as described in steps (2) and (3) using the
2305. Finally repeat step (4) with the RF LEVEL setting reduced to -7 dBm, readings
should remain unchanged.
46881—-891U
. Oct. 88 5-21
PERFORMANCE TESTING
External modulation (ALC ON)
12. TEST EQUIPMENT 2022E PERFORMANCE DATA
(a)Modulation Meter 2305 Input level: Deviation is calibrated for
inputlevels between 0.9 V and
(e)True RMS Voltmeter
2610 1.1 V RMS. HI or LO on display
indicate if outside this range.
(f) AF Signal Source (low
Freq. response: AM +3 dB from 20Hz to 50kHz
distortion
(relative to FM +1.5 dB from 50Hz to 80kHz
1kHz mod. @m --1 dB from 50Hz to 10kHz.
with ALC ON)
2022€
SIGNAL GENERATOR
; a365 2610
| [ Oe =) TRUE RMS VOLTMETER =
e aes PLELELLLL | _O
tc ccce ce M} [co SSS Bas Pee |
) AF SIGNAL SOURCE
| 50 Hz-25kHz (0-9-1-1V) | |
TPE 51958
Fig. 5-8 Test gear arrangement to check external modulation
Procedure
(1)Because AM, FM and ®M external modulation use a common circuit confi-
guration, checking need only be carried out with one type of modulation input.
Connect the test equipment as shown in Fig. 5-8 and set the 2022E controls as
follows :
CARR FREQ: 250 MHz ,
FM/®M : FM so “
Deviation : 250 kHz
MOD ALC_ : ON (LED lit)
(2) Apply a 1 kHz, 1.00 V RMS input from a low distortion AF signal source to
the 2022E MOD IN-OUT socket.
(3) On the 2305 select the 10 - 300 kHz filter and FM function key. Check that
the displayed FM deviation reading is within specification.
(4) Vary the input voltage between 0.9 V and 1.1 V and check that the modulation
display does not indicate either a HI or LO message. Also check that the deviation
remains constant over the range.
(5) Select 2305 REL function key and vary the frequency of the external mod.
signal between 50 Hz and 80 kfiz. Check that the deviation remains within +1.5
dB of the value set at 1 kHz mod. frequency. oO
46881-891U
Oct. 88
5-22
PERFORMANCE TESTING
(6) Set the 2022E to 80% AM EXT and ALC ON. Return the AF source fre-
quency to 1 kHz and set the 2305 to monitor AM, absolute, noise average.
(7) Select 2305 REL function. Vary the frequency of the AF source signal be-
tween 20 Hz and 50 kHz and check that the deviation remains within +3 dB of the
value set at 1 kHz modulation frequency.
External modulation (ALC off)
13. (1) Connect test equipment as shown in the Fig. 5-8. Maintain 2022E settings
with the exception of the MOD ALC key. Press this to disable the ALC (adjacent
LED should be extinguished).
(2) Select 2305 ABS function key and apply a 1 kHz, 1.00 V RMS signal to the
MOD. IN-OUT socket of the 2022E. Check that the FM deviation displayed on the
2305 is within specification.
46881-891U
Oct. 88 5-23
by, Se SAS aS Ee, Cry CAN TE Rk rep tN ge ogg ELAPSED AN ae URE Me a mee ee en
PERFORMANCE TESTING
Auxiliary modulation
14. TEST EQUIPMENT 2022E PERFORMANCE DATA
(a)Modulation Meter 2305 A rear panel BNC socket provides an
(f) AF Signal Source auxiliary modulation input with a nominal
sensitivity of 20% of the set modulation
deviation/depth for a 1 V PD input.
Input impedance 600 Q nominal.
AF SIGNAL SOURCE
2305
MOOULATION METER
Fig. 5-9 Test gear arrangement to check auxiliary modulation
Procedure
(1) Connect the test equipment as shown in Fig. 5-9.
(2) Set the AF signal source to give a frequency of 1 kHz at 1.00 V RMS.
(3) Set the 2022E controls as follows :
CARR FREQ: 100 MHz ;
RF : 0 dB i
FM : 50 kHz
: EXT
MOD ALC : OFF (LED OFF)
(4) Set the 2305 controls as follows:—
AUTOTUNE
300 Hz - 3.4 kHz FILTER
DE-EMPHASIS : OFF
FUNCTION _ : EM, ABS, a
(5) Check that the 2305 indicates a nominal deviation of 1 kHz.
46881-891U
ome Oct. 88
PERFORMANCE TESTING -
VSWR (50 kHz - 350 MHz)
15. TEST EQUIPMENT 2022E PERFORMANCE DATA
(g) RF Millivoltmeter TF 2603 VSWR: <1.5:1 for all output levels
(h) T connector, TM 7984
(i)N type 50 Q load TM 7967
TF2603
2022€
SIGNAL GENERATOR RF MILLIVOLTMETER
Lou ELLE LL
te CLLEL Lo
Occ LEtLe Loe ©)
Tepe 5189 Ls
T connector
502N type load
Fig. 5-10 Test gear arrangement to check VSWR up to 350 MHz
Procedure
(1) Connect test equipment as shown in Fig. 5-10 and set the 2022E controls as
follows :
CARR FREQ: 100 MHz
RF LEVEL : -10 dBm (70.7 mV PD)
a ) (2) With the 50 Q load disconnected note the reading in the TF 2603.
(3) Now insert the 50 Q load and note the new reading. The impedance, Z, iS
calculated using the following formula,
z =F _s0Q
Vv
where E = open circuit output level
and V_ = output across the 50 Q load.
Z 50
From the above, VSWR = aa one should be better than 1.5:1.
46881-891U
Oct. 88 5-25
PERFORMANCE TESTING
VSWR (above 350 MHz)
16. TEST EQUIPMENT 2022E PERFORMANCE DATA
(j) Short circuit monitor VSWR: <1.5:1 for all output levels
(k) 20 cm Air spaced line GR 874—L20
(1) 20 cm Adjustable line GR 874-LK20L
(m) DC microvoltmeter
2022€
SIGNAL GENERATOR ADJUSTABLE
LINE SHORT CIRCUIT DC MICROVOLTMETER
DETECTOR
LLLL LL Co J
LLL oo
Fig. 5-11 Test gear arrangement to check VSWR above 350 MHz ene. 4
(1) Connect the test equipment as shown in Fig. 5-11 and set the 2022E controls
as follows :
CARR FREQ: 500 MHz
RE LEVEL : -10 dBm (70 mV)
(2) Set the adjustable line to \/2. of the signal by applying the formula
x4 300
where \.is the wavelength in metres
and f is the frequency in MHz.
For example, at 500 MHz, X= sn = 0.6 m
therefore \/2 = 30 cm
(3) Adjust the line length for maximum indication on the meter and note the read-
ing. Adjust the line length for minimum indication on the meter (\/4).
Note ...
The short circuit current monitor uses a diode to detect the maximum and
minimum values (Vmax. and Vmin.) This diode is being used at the lowest
part of its characteristic and the square law applies.
The VSWR is therefore equal to / Vmax. and should be better than 1.5:1.
46881-891U
es Oct. 88
PERFORMANCE TESTING
Carrier harmonics and sub-harmonics
17. TEST EQUIPMENT 2022E PERFORMANCE DATA
(n) Spectrum analyzer 1. Harmonically related Better than -25 dBc.
signals for output
levels up to +10 dBm.
2. Sub-—harmonics for None for carrier
output levels below freqs. below 500 MHz.
+10 dBm. —25 dBc above 50MHz.
3. Non—-harmonically <-70 dBc for carrier
‘ related signals for freqs. of 62.5MHz and
] output levels below above.
+10 dBm. <-60 dBc below
62 .5MHz.
2022E
SIGNAL GENERATOR SPECTRUM ANALYZER
Lt ELLLt LL
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Fig. 5-12 Test gear arrangement to check carrier harmonics and sub-harmonics
Procedure
(1) Connect the test equipment as shown in Fig. 5-12 and set the 2022E controls
as follows :
RF LEVEL : 10 dBm
CARR FREQ: 15 MHz
AM,FM,®M : OFF
(2) The spectrum analyzer used should be capable of measuring at least the 3rd
harmonic of the carrier frequency. Check that the amplitude of any harmonic does
not exceed specification at carrier frequencies of 15, 63, 126, 252, 300 and 500
MHz: Repeat above checks with further RF level settings of 0 dBm and —7 dBm.
The carrier frequencies selected will check for harmonics in the following circuits :
15 MHz BFO band
63 MHz Incorporates two stages of freq. divisio
126 MHz Uses a single divider stage :
252 MHz Fundamental band
300 MHz Checks the tracking of the tuning notch
350 MHz 99 29 39 9 9 39 ”
500 MHz Doubler band
46881-891U
Oct. 88 5-27
PERFORMANCE TESTING ite
(3) Sub-harmonics are only produced when carrier frequencies above 500 MHz
are selected. Check at the three RF level settings given (+10 dBm, 0 dBm and -7
dBm) that the sub-harmonics do not exceed specifications at each of the following
carrier frequencies : 501 MHz, 700 MHz, 900 MHz and 1000 MHz.
46881-891U
Oct. 88
PERFORMANCE TESTING
Residual FM
18. TEST EQUIPMENT 2022E PERFORMANCE DATA
(a)Modulation Meter Residual FM
(q) Low noise signal (FM OFF): <7 Hz RMS (10 Hz equivalent
generator peak) deviation in a 300 Hz to
(s)2 MHz low-pass filter 3 kHz bandwidth at 499 MHz and
improving by 6 dB per octave
with reducing carrier frequency
down to 62.5 MHz.
<3.5 Hz RMS (5 Hz equivalent
peak) below 62.5 MHz.
Note ...
Owing to the low residual specification of the 2022E the FM residual measurement
system should have a typical residual noise figure of less than 1.5 Hz up to 500 MHz
and 2.5 Hz up to 1000 MHz. (The following set-up makes use of the low noise low
frequency end of the 2305.)
2017
AM/FM SIGNAL GENERATOR
2305
MODULATION METER
Mixer 2 MHz LPF TPB $772A
Fig. 5-13 Test gear arrangement to check residual FM
Procedure
(1) Connect the equipment as shown.
(2) Set the 2305 controls as follows: FM, absolute, 300 Hz to 3.4 kHz filter, noise
average.
(3) Set the 2022E to give a carrier frequency of 499 MHz, RF LEVEL 0 dBm, FM
OFF.
(4) Set the 2017 to give a carrier frequency of 500 MHz, RF LEVEL 0 dBm, FM
OFF. |
Note ...
The 2017 should always be set 1 MHz higher than the frequency set on the
2022E.
46881-891U
Oct. 88 5-29
5-30
PERFORMANCE TESTING
(5) Check that the residual FM reading on the modulation meter is 10 Hz or less.
(6) Set the 2022E frequency to 62 MHz and the 2017 frequency to 63 MHz and
check that the residual FM reading on the modulation meter is 5 Hz or less.
(7) Set the 2022E frequency to 1000 MHz and the 2017 frequency to 1001 MHz
and check that the residual FM reading on the modulation meter is 20 Hz or less.
46881-891U
Oct. 88
5
PERFORMANCE TESTING
Reverse power protection
19. TEST EQUIPMENT 2022E PERFORMANCE DATA
(e) True RMS Voltmeter 2610 Protection: The generator output is pro-
(o) Variable DC power supply tected against reverse power of
TF 2158 up to 25 W from a source VSWR
5:1 from DC to 1.01 GHz.
Procedure
(1) Switch the 2022E on so as to internally connect the RF OUTPUT socket of the
instrument. Set the RF LEVEL to 0 dBm (this will protect the resistors in the
attenuator in the event of an RPP malfunction). Then set the DC power supply to
+5 V and apply this to the 2022E RF OUTPUT 50 Q socket causing the RPP circuit
to trip (taking care not to damage the connector pin).
(2) An indication that the reverse power unit has been tripped will now be given
by the REV PWR annunciator which will flash on the RF LEVEL display.
(3) Remove the +5 V source and check that there is no continuity between the ‘N’
type connector centre pin and earth (again taking care not to damage the connector
pin). If the RPP has not tripped, a resistance of approximately 1 kQ may be
measured between the centre pin and earth.
(4) Reset the RPP by pressing the RF LEVEL key and ensure that the REV PWR
indication is now off. Set the DC power supply to -5 V and apply this again to the
RF OUTPUT 50 Q socket checking that the RPP trips once more. Remove the DC
source and reset the RPP.
(5) Operation of the RPP trip circuit can also be checked if required without the
application of a voltage to the RF OUTPUT 50 Q socket using Second function 3
(Manual latch setting). Access to the attenuator latch for ACO and the means of
entering the necessary data to achieve this is described in para. 6. Setting a binary
‘1’ level in D5 (see Table 5-3) will cause the RPP to trip.
46881-891U
Oct. 88 5-31
5-32
PERFORMANCE TESTING
THIS PAGE INTENTIONALLY LEFT BLANK.
46881-891U
Oct. 88
bows
‘.
aw
wil
ee
Chapter 5-2
ADJUSTMENT AND CALIBRATION
CONTENTS
1 Introduction
5 Second function ‘191’ FM tracking calibration
6 Second function ‘192’ RF level calibration
7 Second function ‘193’ Voltage tuned filters (VIF) calibration
8 Second function ‘194’ AM calibration
9 Second function ‘195’ Calibration and storage of amended EAROM checksum
0 EAROM initialization
1 External frequency standard adjustment (1, 5 or 10 MHz)
Page
5-4 Realignment order
5-5 A1/2 Keyboard and display board alignment ..
5-6 A2/2 Power supply and control board alignment
5-7 AA1/1 Synthesizer board alignment ... ei
5-8 AA2/1 Microprocessor board alignment
5-9 AB1/2 RF processing board alignment
5-10 Attenuator assembly alignment
5-13 External frequency standard adjustment
46881-891U
Mnte 020
34
38
39
42
42
42
44
44
ADJUSTMENT AND CALIBRATION
INTRODUCTION
1. This chapter describes adjustments which will restore the instrument to its peak
operating condition. Test equipment recommended for this purpose is listed in Chap. 5-0
and summarized for board test procedure. Before carrying out any adjustment
procedures refer to Chap. 5-0 for safety considerations and access instructions.
2. Information is given for the overall realignment of the instrument with details of
preset components, affected circuits and the use of second function controls where these
are needed in recalibration procedures.
3. After completing repairs to a circuit or replacement of a board it may be necessary
to carry out realignment. If a full overall realignment is required it should be carried out
in the order shown in Table 5-4 below.
TABLE 5-4 REALIGNMENT ORDER
Order Adjustment Table of reference 2ND FUNCT
1 Set +12 V 5-7 None
+5 V 5-7 None
3 -12 V 5-7 None
4 +24 V 5-7 None
b +21 V 5-9 None
6 LCD off 5-6 None
7 Internal audio level 5-8 None
8 250 MHz 5-10 None
9 353 MHz 5-10 None
10 160 MHz 5-10 None
11 160 MHz ‘LF AM Mod’. 5-10 None
12 Correct jitter S-7 None
13. Cal. band-pass tracking 5-7 193
- and Notch 5-10 3
14 Cal. RF power >62.5 MHz 5-7 192
15 Cal. RF power <62.5 MHz 5-7 192
16 Cal. AM >62.5 MHz 5-7 194
17. Cal. AM <62.5 MHz 5-7 194
18 External mod. 5-6 None
19 Set LF FM and 5-6 191
- FM tracking 5-20 191
20 Set ®M 5-6 None
21 Set Int. Std. Freq. 5-6 None
4. If only one board is affected and a full overall realignment procedure is not needed
then the individual board can be realigned with reference to Tables 5-5 to 5-10. Some
of the tables make reference to certain alignment procedures using second functions
191-194. A comprehensive description of these is included in paragraphs 5 to 10.
Note ...
Before any adjustments are made all screening covers should, where possible, be
firmly fitted.
46881-891U
5-34 Oct. &8
ADJUSTMENT AND CALIBRATION
Second function ‘191’ FM tracking calibration
5. The FM tracking calibration data comprises two tables of calibration points. These are
listed in Table 5~20 (Chap. 5-3). To enter data, carry out the following procedure :
(1) Unlock the instrument to allow second level operation.
(2) Select CARR FREQ 250 MHz and a carrier frequency increment of 4.12 MHz,
FM INT, 99.9 kHz.
(3) Enter 2ND FUNCT 191.
(4) Monitor the actual deviation obtained on a modulation meter (2305). If no
data has been stored, enter the value shown in Table 5-20, e.g. 194. Now using the
up (t) or down (|) key adjust the calibration data until the modulation meter reads
closest to the value 99.9 kHz and press the STORE key, (see following Notes before
calibrating). 7
(5) Reselect CARR FREQ followed by the up key to increment the carrier
frequency by 4.12 MHz. Re-enter IND FUNCT 191 and the approximate data,
(e.g. 204) then adjust the value using the up or down key as described in step (4)
and STORE. Repeat the above procedure for succeeding 4.12 MHz increments
entering data in each until reaching a carrier frequency of 353 MHz. At this point
reselect CARR FREQ 352.999 MHz, 2ND FUNCT 191, enter data and STORE.
(6) Select CARR FREQ, 353 MHz and a carrier frequency increment of 5.88 MHz,
re-enter 2ND FUNCT 191 then continue entering data as previously described in
steps (4) & (5) until reaching a carrier frequency of 500 MHz. At this point select
instead CARR FREQ 499.9999 MHz, re-enter IND FUNCT 191, enter data and
STORE. This completes the FM tracking.
Notes ...
(1) The audio frequency response must have previously been adjusted using A2/2 R58,
‘SET LF FM’.
(2) A suitable bandwidth must be selected on the modulation meter to avoid errors due
to demodulated noise e.g. (50 Hz - 15 kHz).
Second function ‘192’ RF level calibration
6. The RE level is calibrated at 11 selected reference points, each point is numbered
from 00 to 10 with the selected point displayed in the modulation window. Calibration is
carried out first at 15 MHz and then in 100 MHz steps from 100 to 1000 MHz.
(1) Unlock the instrument to allow second level operation.
(2) Select CARR FREQ, 15 MHz, RF LEVEL, 42.9 dBm and an RF level incre-
ment of 9.9 dB.
(3) Enter 2ND FUNCT 192.
(4) Monitor the RF OUTPUT using a Power Meter (6960) and Power Sensor
(6912). |
46881-891U .
min 00 5-35
ADJUSTMENT AND CALIBRATION
(5) Enter a value of data that will give a reading of +2.9 dBm on the power meter
using the up or down keys as required (there is no auto incrementing on this
function).
(6) Select RF LEVEL then the down key to obtain a level of -7 dBm; adjust AB1/2
R101, “LF ALC LOW’ for a 9.9 dB difference between this reading and that
obtained in step (5), (dB rel. key can be used on 6960). Reselect the up key to
obtain 2.9 dBm output and iterate until the values obtained in step (5) and (6) are as
close to 2.9 dBm and -7 dBm as possible, then STORE the calibration data.
(7) Select CARR FREQ, 200 MHz and a carrier frequency increment of 100 MHz,
RF LEVEL, 2.9 dBm. Now repeat the procedure. described in steps. (4) and (5)
decrementing the level to -7 dBm and in this case adjusting A2/2 R84, ‘HF ALC
LOW’ to obtain the 9.9 dB difference.
(8) Select CARR FREQ and using the down key decrement the carrier frequency
to 100 MHz, select RF LEVEL, 2.9 dBm. Re-enter 2ND FUNCT 192 followed by a
value of data to obtain a reading of 2.9 dBm on the power meter then STORE. Now
select CARR FREQ and with the up key increment the carrier to select a frequency
of 300 MHz. Re-enter 2ND FUNCT 192 and enter data to give a power meter
reading of 2.9 dBm and STORE. Continue to increment the carrier frequency in
100 MHz steps entering data and storing in each case until reaching the last data
point, 10 (1000 MHz). This completes the RF level calibration.
Second function ‘193’ voltage tuned filters (VTF) calibration.
ds
The VIF or Output harmonic control calibration table consists of 6 points cali-
brated in 100 MHz steps from 500 MHz to 1000 MHz. Each point is numbered from 00
to 0S with the selected data point displayed in the modulation window. Calibration is
carried out as follows:-
5-36
(1) Unlock the instrument to allow second level operation.
(2) Select CARR FREQ, 500 MHz and a carrier frequency increment of 100 MHz.
(3) Monitor AB1/2 ‘ALC HF’ test point with a digital voltmeter.
(4) Enter 2ND FUNCT 193.
(S) Enter or adjust data to obtain the greatest positive reading possible (typically
+10 V), then press the STORE key to terminate the entry. Typical values of cali-
bration data expected can be seen in Table 5-21 (Chap. 5-3). Values of voltage
shown in that table however cannot be compared because they are taken from a
different circuit reference.
(6) Select CARR FREQ followed by the up key to select a carrier frequency of 600
MHz. Repeat the procedure described from step (4) and continue the calibration
for each step unti! reaching the !ast data point, 05 (1000 MHz). This completes the
VTF calibration.
46881-891
Oct. £
ADJUSTMENT AND CALIBRATION
Second function ‘194’ AM calibration
8. Only two points are calibrated. At point 00 data is entered at a carrier frequency
of 15 MHz and point 01 at a carrier frequency of 100 MHz. 00 or 01 is displayed in the
modulation window after selecting 2ND FUNCT 194 and the relevant carrier frequency.
Calibrate as follows:-
(1) Unlock the instrument to allow second level operation.
(2) Select CARR FREQ, 15 MHz, AM, INT, 95%, RF LEVEL, +3 dBm.
(3) Monitor the RF OUTPUT socket using a modulation meter (2305).
(4) Enter 2ND FUNCT 194.
(5) Enter or adjust data to obtain a mod. meter reading of 95% then STORE to
terminate the entry.
(6) Select CARR FREQ, 200 MHz, AM, INT, 90% and an REF level increment of
9.9 dB.
(7) Again enter 2ND FUNCT 194 and enter or adjust data to obtain a reading on
the mod. meter of 90% then STORE the value.
(8) Select RF LEVEL followed by the down key to give a power level reading of
-6.9 dBm. Adjust A2/2 R90 ‘CORRECT DETECTOR’ to give a mod. meter
reading of 90% AM. Reselect up and down keys and repeat the adjustment until a
reading of 90% is obtained at both 6 dBm and -6.9 dBm. This completes the AM
calibration.
Second function ‘195’ calculation and storage of amended EAROM
checksum
9. If the instrument has been recalibrated, or if data in the EAROM, AA2/1 IC10, has
been accidentally erased, or if an unserviceable EAROM has been replaced then a new
checksum should be stored and initialization should be carried out. When recalibrating
the instrument following EAROM replacement it should not be necessary to adjust any of
the internal preset components; calibration data can be found by accessing the data from
the front panel second function controls and in the following order 191,193,192,194.
Enter the calibration information for each of the above second functions and store in each
case. When this is completed select 2ND FUNCT 195 and STORE. The instrument will
re-calculate the checksum, store this in the non-volatile memory and display 000 to
indicate completion.
EAROM initialization
10. Data stored within the EAROM but not part of the checksum will also have to be
re-entered. A replacement EAROM is normally supplied with all “1’s stored, therefore
flags on most second functions and other settings referred to have been arranged such
that the most useful are selected when a replacement EAROM is installed. Each of the
following should be checked, re-entered if necessary, depending on individual user
requirements, and in the order given below.
46881-891U
Oct. 88 5-37
ADJUSTMENT AND CALIBRATION
(1) RF level offsets data (second function 15) off ‘0’ on ‘1’. This facility must not
be used until the instrument is calibrated.
(2) Checksum data for calibration values (second function 195).
(3) Timer information, both for the resettable (second function 9) and the fixed
timer (second function 199) — see Note below.
(4) ‘Identity strings (second function 190) - Chap. 4 para. 191 refers. These can
be recalled using either second functions 5 or 11.
(5) User defined strings entered by means of second function 12.
(6) Instrument settings stored by the user. Store protection (second function 196)
and Display blanking of recalled stores (second function 197). Each store has a
separate checksum which is automatically entered on storing a valid setting. Stores
not having a value entered will initiate a EAROM recall error message 15 when
recalled.
(7) Calibration information from second functions 191-194.
‘8) External frequency standard 10,5 or 1 MHz (second function 10).
9) If the optional GPIB facility is fitted set the address as required (second
inction 2).
e total instrument operating time indicator, if accessed by secondfunction 198 will
‘bably read 131, 071 hours. After approximately 15 minutes instrument running
e this will overflow and reset to 0 hours.
TABLE 5-5 A1i/2 KEYBOARD AND DISPLAY BOARD ALIGNMENT
lent Test equipment Method Adjustment window/Comments
Visual examina— Adjust R2 whilst Some contrast may be lost
. tion only observing the if incorrectly adjusted.
required. segment of the
display from an
acute angle.
Adjust so that
‘off’ segments
are barely
turned off.
46881-891U
Oct. 88
ADJUSTMENT AND CALIBRATION
TABLE 5-6 A2/2 POWER SUPPLY AND CONTROL BOARD ALIGNMENT
Adjustment Test equipment
RS DVM
‘Set +12 V’
R15 DVM
‘Set +5 V’
R8 DVM
‘Set -12 V’
R89 DVM
R67 Modulation
‘Correct meter connected
Jitter’ to a spectrum
analyzer.
‘Cal. band- DVM
pass filter’
‘Cal. RF power RF power meter
and R84
HF ALC low’
46881-891U
Oct. 88
Method
Detach all board
external loads
and adjust to
412.1 V
Detach all board
external loads
and adjust to
+5.05 V
Detach all board
external loads
and adjust to
-12.1 V.
Detach all board
external loads
and adjust to
+24.25 V.
Select CARR FREQ,
250.0005 MHz.
Look for a tone
and null this.
Select CARR FREQ,
500 MHz Monitor
‘ALC HF’ test
point on AB1/2.
Adjust CAL DATA
(using 2ND FUNCT
193) for greatest
positive reading.
Repeat at 100 MHz
intervals up to 1 GHz.
Select CARR FREQ,
200 MHz,RF LEVEL
+2.9 dBm. Adjust for
+2.9 dBm output
(using 2ND FUNCT
192). Select RF LEVEL
-7 dBm and adjust
R84 then optimize
Adjustment window/Comments
+0.1 V
+0.05 V
+0.1 V
+0.25 V
If this is incorrectly set
there may be additional co-
herent signals present with
the carrier frequency.
Increments are extremely
fine and a setting within -
+5 counts will give
adequate results.
Adjust R84 to give a 9.9 dB
difference between the
2.9 dBm and -7 dBm
readings at 200 MHz.
with +2.9 dBm adjust-
ment. Finally calibrate
at 100 MHz and sub-
sequent 100 MHz
intervals up to 1 GHz.
ADJUSTMENT AND CALIBRATION
TABLE 5-6 A2/2 POWER SUPPLY AND CONTROL BOARD ALIGNMENT (conid.)
Adjustment Test equipment Method Adjustment window/Comments
‘Cal. AM Modulation Select CARR FREQ,
>62.5 MHz’ meter 200 MHz, RF
and R90 LEVEL,6 dBm,AM,
Correct AM 80%. Adjust
det’. (using 2ND FUNCT
194) until reading
is correct.
Select RF LEVEL,
-6.9 dBm,AM,90%
and adjust R90 for
correct AM depth.
Re-check cal. data
setting at 6 dBm.
‘Cal. RF Power meter Select CARR FREQ, It is unlikely that there
power’ and 15 MHz, RF LEVEL, will be a significant dif-
R101 (AB1/1) 2.9 dBm. Adjust ference in the calibration
‘LF ALC low’ (using 2ND FUNCT data.
192) cal. data for
2.9 dBm output.
Select RF LEVEL,
~7 dBm and adjust
R101 (AB1/2) for
-9.9 dB w.r.t.
2.9 dBm reading.
Recheck the
2.9 dBm setting.
‘Cal. AM Modulation Select CARR FREQ, It is unlikely that a
<62.5 MHz’ meter. 15 MHz, RF LEVEL, significant change in cal.
+3 dBm, AM, 95%. data will be required.
Adjust (using 2ND
FUNCT 194) for
correct value.
R113
‘External Modulation Select CARR FREQ,
Mod?’ meter. Accurate 250 MHz, FM dev.,
1 V RMS 99.9 kHz. Apply
1 kHz external Ext. Mod. source,
source. MOD ALC on. Note
the reading. Switch
MOD ALC off and
adjust R113 for iden-
tical dev.reading.
Recheck MOD ALC
on reading.
46881-891U
Oct. 88
REET,
ADJUSTMENT AND CALIBRATION
TABLE 5-6 A2/2 POWER SUPPLY AND CONTROL BOARD ALIGNMENT (contd.)
Adjustment Test equipment
‘Cal. FM and Modulation
R58 Set meter and
LF FM’ Audio source
100 Hz,0 kHz,
1 V RMS.
R56 Modulation
‘Set ODM’ meter
(A0/1)R1 Frequency
‘Int. Std. counter
Adjust’.
46881-897U
Ort RR
Method
Select CARR FREQ,
250 MHz, FM dev.
99.9 kHz. Apply
10 kHz Ext. Mod.
source, MOD ALC
on. Adjust cal.
data (using 2ND
FUNCT 191) for
99.9 kHz dev.
Now set Ext. Mod.
source to 100 Hz
and adjust R58
for 99.9 kHz dev.
Remove Ext. Mod.
source and select
Int. Mod. and re-
calibrate at fre-
quencies shown in
Table 5-20.
Select CARR FREQ,
250 MHz, ®M 9.99
rads. dev. Adjust
R56 for the same
reading.
Adjust A0/R1 for
correct reading.
Adjustment window/Comments
If calibration number does
not change by more than
one or two digits, check
to see if FM is within
specification before
proceeding with re-
calibration.
Can be demodulated as FM
and dev. set to 9.99 kHz.
1 kHz internal source
frequency is extremely
accurate.
2022E frequency accuracy
is directly dependent on
this setting.
ADJUSTMENT AND CALIBRATION
TABLE 5-7 AAi/1 SYNTHESIZER BOARD ALIGNMENT
Adjustment Test equipment Method
R43 AC Select 1 kHz INT
‘Set audio voltmeter MOD and monitor
level’ the voltage on the
MOD IN/OUT
socket. Adjust R81
for 1.00 V RMS.
(A0/1)R1 Adjustment carried out in conjunction
‘Int. Std. with A2/2 board alignment -
Adjust’. see Table 5-6.
(A2/2)R67 Adjustment carried out in con—-
‘Correct junction with A2/2 board
jitter’ alignment — see Table 5-6.
(A2/2)R58 Adjustment carried out in con-
‘Set LF FM’ junction with A2/2 board
alignment — see Table 5-6.
TABLE 5-8
Adjustment Test equipment Method
R1 Digital Monitor TP1 and
‘Set +4.5 V’
Adjustment window/Comments
Allows for variations in
component value.
Allows for variations in
component value.
AA2/1 MICROPROCESSOR BOARD ALIGNMENT
Adjustment window/Comments
Between +4.5 and +4.55 V.
Should not be necessary to
re-adjust preset controls if
this is the only requirement.
Adjustment window/Comments
+0.1 V
+0.1 V
voltmeter adjust R1 for
44.5 V.
EAROM All recalibration data relating to
Recalibration second functions 191,192,193
and 194.
TABLE 5-9 AB1/1 RF PROCESSING BOARD ALIGNMENT
Adjustment Test equipment Method
C38 Digital Select CARR FREQ,
‘250 MHz’ voltmeter 250 MHz. Adjust
C38 for 2.0 V on
PLAD pin 16.
C31 Digital Select CARR FREQ,
*353 MHz’ voltmeter 33 MHz. Adjust
(carrier C31 for 2.0 V on
frequency) PLAD pin 16.
46881-891U
Oct. 83
ADJUSTMENT AND CALIBRATION
TABLE 5-9 AB1/1 RF PROCESSING BOARD ALIGNMENT (contd.)
Adjustment
C7
‘160 MHz’
C18
‘LF AM MOD’
‘Cal FM and
(A2/2)R58
Set LF FM’
‘Cal RF power
and (A2/2)R84
HF ALC low’
‘Cal RF power
and R101
LF ALC low’
‘Cal band-pass
filter and L13
notch’
C16
‘LE AM mod.’
46881-891U
Oct. 88
Test equipment
Digital
voltmeter
Digital
voltmeter
Method
Select CARR FREQ,
10 MHz. Adjust
C7 for 12.0 V on
PLAD pin 1.
Select CARR FREQ,
10 MHz RF LEVEL,
0 dBm. Connect
DVM to ALC LF
test point and adjust
C18 for maximum
positive voltage.
See A2/2 board alignment
(Table 5-6)
See A2/2 board alignment
(Table 5-6)
See A2/2 board alignment
(Table 5-6)
Digital volt-
meter and
500 MHz
Spectrum
Analyzer
Digital
voltmeter
Calibrate band-pass
filter (see A2/2 board
alignment). Note
calibration value at
500 MHz. Select
CARR FREQ,
499 MHz,RF LEVEL,
+6 dBm, (using
2ND FUNCT 3
address[12]) enter
value noted above
into the filter
tracking DAC.
Adjust L13 for
minimum output
at 499 MHz.
Select CARR FREQ
15 MHz. Monitor
‘ALC LF’ test point
and adjust for
maximum reading.
Adjustment window/Comments
+1 V
Nominally +6 V to +7 V.
There will be some effect
due to hand capacitance
although the adjustment
is not critical. Should
obtain typically 20 dB
rejection from the notch.
The voltage measured will
depend on the RF LEVEL
selected.
ADJUSTMENT AND CALIBRATION
TABLE 5-9 AB1/1 RF PROCESSING BOARD ALIGNMENT (contd.)
Adjustment Test equipment Method Adjustment window/Comments
‘Cal. AM See A2/2 board alignment |
>62.5 MHz (Table 5-6)
and (A2/2)R90
Correct det’
‘Cal AM See A2/2 board alignment
<62.5 MHz’ (Table 5-6)
TABLE 5-10 ATTENUATOR ASSEMBLY ALIGNMENT
Adjustment Test equipment Method Adjustment window/Comments
‘CAL RF Power meter Select CARR FREQ, No attempt should be made
power’ 15 MHz, 100, 200, to adjust the frequency
300, 400, 500, 600, compensation screws on
700, 800, 900 and The attenuator assembly.
1000 MHz, RF Refer to factory.
LEVEL, 0 dBm.
Adjust cal. data
(using 2ND
FUNCT 192) to
give 0 dBm output.
External frequency standard adjustment (1, 5 or 10 MHz)
11. One of three external standard frequencies may be used providing a link on AA1/1
board is correctly positioned. Fig. S-13 shows the position of the three link positions for
1,5 or 10 MHz. Withdraw the link manually from the board (normally selected to 10
MHz) and reposition as required. On completion apply power and using ZND FUNCT 10
record the current selection and STORE. Further check by selecting 2ND FUNCT 1
‘Status’ mode that the correct reading is evident in the modulation window.
a ae a a on os my
= ne as ae es al
Fig. 5-13 External frequency standard adjustment (1, 5 or 10 MHz)
46881-891U
5-44 Oct. 88
veneer
Chapter 5-3
FAULT LOCATION
CONTENTS
Para
1 Introduction
5 Fault finding to board level
7 Front panel failure
15 Output frequency error
23 RF level errors
35 AM faults
Al FM and &M faults
51 Excessive carrier harmonics
59 GPIB faults
62 Manual latch setting
63 Data entry
69 Fault finding to component level
75 Display and keyboard (A1/2)
81 Power supplies, modulation control and data conversion (A2/2)
94 Power supply/control latch address data
95 Frequency synthesizer and internal modulation source (AA1/1)
112 Microprocessor (AA2/1)
118 RF processing board (AB1/2)
Table
5-11‘ Front panel failures
5-12 Error messages (AA2/1)
5-13 Processor machine cycle status (AA2/1)
5-14 Output frequency error
5-15 AB1/2 contro! data
5-16 Frequency latch setting data
5-17 _ RF level errors
5-18 AM depth errors
5-19 FM deviation errors
5-20 Typical FM tracking data
5-21 Typical calibration data and drive ‘voltages ‘for AB1/2 band- _pass ‘filter
5-22 2022E latch addresses.. an ai dig
5-23 Display and keyboard latch address data
5-24 Power supply/Control latch address data
5-25 Frequency synthesizer latch address data
5-26 Synthesizer frequency address decoder outputs
5-27 Data latch increment sequence ...
5-28 Typical band-pass filter tracking voltages/calibration data
5-29 62.5-1010 MHz output amplifier drive conditions
5-30 Frequency band switching, logic levels
Fig.
5-14 Voltage test points :
5-15 Data transfer between boards
5-16 Backplane drive waveforms and test locations
5-17. Effect of square-law correction circuit A2/2
5-18 160 MHz phase detector IC6, timing signals
5-19 Synthesizer drive and control waveforms
46881-891U
Oct. 88
FAULT LOCATION
INTRODUCTION
1. This chapter deals with diagnostic procedures and tests to aid fault localization.
Information is given in three groups:—
(1) Fault finding to board level from front panel symptoms and error messages,
followed by diagnostic charts for each functional area of the instrument.
(2) Manual latch setting procedures for entering binary data to specified latches,
allowing diagnosis of internal bus or latch faults.
(3) Fault finding to component level, giving test data and procedures for each
board.
2. The functions of each board are generally well defined and independent of each
other as far as possible. The recommended method of confirming a board fault is to sub-
stitute a known good board (e.g. from a spare serviceable instrument). This can save
considerable fault finding time.
3. Easily accessible test points are provided on the boards to allow you to quickly
confirm that voltage rails are correct. These are simply solder pads with a central hole
surrounded by a white circle. The nominal voltage expected at that point is also
indicated as shown in Fig. 5-14.
4. Test equipment recommended for fault finding is listed in Chap. 5-0. Before
carrying out any internal operations refer to Chap. 5-0 for safety considerations and
access instructions.
FAULT FINDING TO BOARD LEVEL
5. The following section describes fault finding routines using tables which may be
used to help diagnose faults down to board level. The fault finding routines start from a
generalized fault condition and guide you to the most likely area of the fault. The
generalized fault conditions used as a Starting point are as follows:
(a) Front panel failure
(b) Output frequency error
(c) Output RF level error
(d) RPP failure «
(e) AM fault —
(f) FM/®M fault
(g) Residual noise on carrier frequency
(h) Excessive carrier harmonics
(i) GPIB fault
46881-891U
5-46 Oct. 88
lean
FAULT LOCATION
17. The following boards are those that are concerned with the generation of the output
frequency and could be at fault.
AAI/1 — Synthesizer
AB1/2 RF signal processing
A2/2 Power supply/Control
AA2/1 — Microprocessor
18. Before carrying out extensive tests on a board check the following connectors which
could be at fault:
SKV —- SKW 160 MHz sync from AB1/2 to AA1/1
SKY - SKZ 250-500 MHz sync from AB1/2 to AA1/1
PLAB Microprocessor to synthesizer
PLM - PLAD - A2/2, Control to AB1/2
19. Signal frequency faults can be divided broadly into three categories:
(1) RF signal. processing — division, multiplication or mixing
(2) Frequency synthesis
(3) Variations in the reference frequency
Initially it is advisable to begin by checking the fundamental octave, 250-500 MHz. If
this is not where the fault lies, suspect a category (1) fault.
20. Box A (see Table 5-14) AB1/2 control lines. Select and switch between the two
carrier frequency settings shown in Table 5-15. Switching between the two should
cause all four bits of data to change. If the frequency is not correct on the
fundamental band suspect either the synthesizer or reference frequency standard,
depending on the size of the error.
TABLE 5-15 AB1/2 CONTROL DATA
Selected AO pin 6 A1/2 pin 11 A2 pin5 OSC HIGH pin 10
frequency (2nd brown lead) (2nd red lead) (White lead) (2nd yellow lead)
10 MHz 0 1 1 0
200 MHz 1 0 0 1
21. Box B (Size of frequency error). With reference to box B, shown in Table 5-14,
two selected frequencies, 471 MHz and 317.4 MHz, are called for. These are
chosen such that only the‘ four modulus divider IC9 on AA1/1 is in use. A “zero”
error implies an error that is within the drift limit of the internal reference frequency
measurement accuracy.
22. Box C (Significant frequencies). The two frequencies chosen here, 252.57365 and
382.3073 MHz, cause all of the frequency setting latch outputs to change state.
First enter 252.5736 MHz and then use a 50 Hz positive increment. STORE this in
location 02. Now enter 382.30730 MHz and STORE in location 03. If RECALL is
now used the increment keys can be used to change rapidly between one setting and
the other. The increment up key will require pressing each time RECALL 02 is
used to set the last 3 bits in IC23 correctly.
46881-891U
Oct. 88 5-53
5-54
TABLE 5-16
Frequency
252.57365 MHz
382.3073 MHz
DATA BIT
IC13
011001
100110
Ds—---Do
FAULT LOCATION
FREQUENCY LATCH SETTING DATA
IC19
01
10
D1----Do
IC3
010101
101010
Ds-—---Do
IC24
010101
101010
Ds----Do
IC23
010101
Ds—-~-Do
46881-891U
Oct. 88
FAULT LOCATION
6. Choose the description that most closely describes the fault condition and use the
fault finding guide to establish the area of the fault. Before using the fault finding tables
read the accompanying notes. The construction of the instrument is such that it should
be possible to locate and correct all faults without resorting to special adapters or ex-
tender cables. Where board exchange is practised or where the repair to a board is such
that recalibration may afterwards be required - see Chap. 5-2, Adjustment and
Calibration.
Front panel failure
7. Achart to aid fault finding in this area is given in Table S-11. A front panel failure
is defined as a fault in which the keyboard or the information given on the LCD and
LEDs is abnormal.
8. The fault is likely to be on one of three boards or the interconnections between
these.
Suspect boards interconnections
AA2/1 Microprocessor AA2/1 (PLAC) -— A2/2 (PLL)
A2/2 Power supply & control A2/2 (PLF) | - Transformer T1
A2/2 (PLH) - A0/1 power devices TR1,IC1
A2/2 (PLK) - Ai/2 (SKK)
A1/2 Keyboard & display board A1/2 (SKK) —- A2/2 (PLK)
Fig. 5-15 shows the format in which data is transferred between boards and Table 5-11
should assist in diagnosing which of the three boards is at fault. Generally information
from the microprocessor is transmitted in serial form to A2/2. Here its format is modi-
fied to suit the device being controlled. The LCD drivers use a special format serial link
whilst the keyboard and LEDs are controlled using a parallel bus.
DISPLAY RESET
Fig. 5-15 Data transfer between boards
CLOCK & STROBE
A1/2
AA2/1 A2/2
DATA
INTERRUPT
KEYBOARD
& DISPLAY
POWER SUPPLY
&CONTROL
MICROPROCESSOR
46881-891U
Oct. 88 5-49
FAULT LOCATION
9. The microprocessor is interrrupt driven, so that key presses need to cause an
interrupt before the processor will take data from A2/2 to check the state of the keyboard.
If the microprocessor is serviceable but a fault exists in the memory, then an error
number may be displayed depending on the location of the fault. Error numbers are
displayed in the carrier frequency window as shown below. Table 5-12 gives details of
/
all available error numbers.
7
Frreoar ib
Fad
rr
TABLE 5-12 ERROR MESSAGES (AA2/1)
Error No. Error condition
01* Request outside limits
02* Incorrect key code sequence
03* Too many digits
04* Incorrect unit
0S* RPP trip
06 RAM check failure (IC12)
07 EAROM checksum failure (IC13)
08 EPROM checksum failure (IC7)
09* External modulation outside ALC range (LOW)
10* External modulation outside ALC range (HIGH)
11 External standard selected but not applied
12 External standard frequency not locking
13 Latch write error
14 EAROM write error
15 EAROM recall error |
16 GPIB bus error as
17 Unrecognized GPIB mnemonic/character
18 Attempt to write to protected store
* These error numbers refer to GPIB error conditions and therefore do not indicate
on the front panel display.
10. Error 06 RAM check failure. This test is carried out by writing a series of ‘1’s and
‘0’s into the RAM - see para. 62 — and then reading them back.
Error 07 EAROM checksum failure. This is carried out by summing the cali-
bration data and a checksum byte. If the result is not FF then error 07 will be
displayed.
Error 08 EPROM check failure. This is similar to the EAROM check. Data that is
stored in memory is also checked. If error 07 is displayed when a store is recalled
it indicates that the stored data has been corrupted.
46881-891U
5-50 Oct. 88
FAULT LOCATION |
FM and oM faults
41. An FM fault finding guide is given in Table 5-19. (It is assumed that the fault
cannot be rectified by simply recalibrating the instrument.) Frequency modulation at
rates greater than 1 kHz is mainly derived by simply applying the signal to the VCO
tuning line. A differentiator in the signal path creates phase modulation (6 dB/octave
pre-emphasis). The deviation that is applied over the fundamental octave is scaled
appropriately for the doubler and divider bands.
42. Angle modulation at low frequencies is achieved by introducing a phase modulator
into the reference signal path of the synthesizer. By integrating the signal driving the
phase modulator an equivalent of frequency modulation is then obtained.
43. The following boards and connectors are possibly connected with an FM or ®M
fault :
Suspect boards Interconnections
A2/2 Modulation control A2/2 (PLM) AB1/2 (SKAD) Signal
from mod. control
AA1/1 Low freq. modulation source A2/2 (PLL) - AA1/1 (PLT) Mod. signal
from AA1/1 to A2/2
AB1/2 FM and VCO drive A2/2 (PLJ) - Modulation in/out
44. Box A (see Table 5-19) Error 7, EAROM checksum error. First check that the
reason for this display is not operator error (EAROM checksum not reset via 2ND
FUNCT 195 after recalibration procedures). Information on the resetting of the EAROM
checksum, if required, is given in Chap. 5-2, para. 9. Assuming that a fault is present it
is most likely to be caused by corruption of data for some reason. As an aid to diagnosing
a fault in the FM tracking store, Table 5-20 gives a list of carrier frequencies used as FM
tracking points together with the typical values of FM tracking data. Normally instruments
will be within approximately 20% of the values listed. There should be no abrupt changes
in value except possibly where the oscillator ranges change over at 353 MHz.
45. In the course of fault finding it may be required to check the input and output levels
of the various digital-to-analogue converters. This can best be carried out using a digital
AC voltmeter and 2ND FUNCT 3 mode to access each IC as required. The latch address
numbers are given both in Chap. 7 and in Table 5-4.
46. Box B (EM level). Set the carrier frequency to 250 MHz, FM 99.9 kHz. Use 2ND
FUNCT 3 to set address 10 to ‘200’. Check that the signal on AB1/2 PLAD pin 12 (black
wire) is 5.2 V p-p.
46881-891U
Oct. 88 5-61
FAULT LOCATION
TABLE 5-20 TYPICAL FM TRACKING DATA
OSC 1 OSC 2
Frequency Data Frequency Data
250 MHz 194 353 MHz 425
254.12 204 358.88 132
258.24 212 364.76 137
262.36 218 370.64 141
266.48 221 376.52 143
270.60 223 382.40 144
274.72 225 388.28 144
278.84 222 394.16 143
282.96 219 400.04 141
287.08 215 405.92 139
291.20 211 411.80 136
295.32 207 417.68 133
299.44 202 423.56 130
303.56 197 429.44 128
307.68 193 435.32 125
311.80 189 441.20 123
315.92 186 447.08 121
320.04 184 452.96 120
324.16 182 458.84 119
328.28 181 464.72 118
332.40 180 470.60 118
336.52 180 476.48 119
340.64 182 482.36 120
344.76 183 488.24 122
348.88 185 494.12 {24 ©
352.9999 189 499.9999 . 127
47. Box C (Frequency response). Apply an external modulation of 1 V RMS ata
frequency first of 1 kHz and then at 100 Hz. If there is a marked difference in the
frequency response between the two then suspect the low frequency modulation path. An
alternative method of checking the reference phase modulator is to examine the AC signal
on the VCO tuning line AB1/2 PLAD pin 16 (red wire). If the EM tracking is set correctly
there should be less than 5 mV p-p of the 1 kHz signal.
Note ...
The 1 kHz MOD IN/OUT output from 2022E can be used to trigger an oscil-
loscope enabling the above to be seen more easily.
48. Box D (Excessive residual FM). If excessive FM is present on the carrier
frequency a higher than normal deviation can be expected. To check for residual noise
set 0 Hz, FM and monitor the output of a low noise modulation meter (2305) set to
measure FM. If noise is excessive follow the additional procedures given in Table 5-19,
and para. 50. :
49. BoxE (LF FM level fault). Select a carrier frequency of 250 MHz and a deviation
of 99.9 kHz. Check at AA1/1 PLT pin 10 (black wire) for a 1 kHz, 150 mV p-p signal.
: 46881-891U
B62, Oct. 88
FAULT LOCATION
50. Box D (Residual noise on carrier frequency). If excessive noise is present on the
carrier frequency several possible sources must be considered. Initially check to assertain
which of the following is the problem source then carry out the necessary remedial action.
(1) AM noise (carrier frequencies above 62.5 MHz). Due to the action of the
levelling loops it is unlikely that changes in amplitude of signals prior to the output
amplifier will be transferred to the final signal. If it is found that the correction
voltage on AB1/2 testpoint “ALC HF” (junction of IC15 pin 6 and R112) is noisy
this is likely to be caused by disturbances on the reference level line. Use an
oscilloscope to check the signal on AB1/2 PLAD pin 3 (green wire). With no AM
applied it should be a DC level free from fluctuations. If not suspect the modulation
control circuit on A2/2 board. To access this remove unit ABO and retrace the
modulation path from A2/2 PLM pin 3.
=, (2) AM noise (carrier frequencies below 62.5 MHz). The response of the
4 levelling loop is extremely slow on this frequency range and because of this noise on
the reference line AB1/2 PLAD pin 3 (green wire) will have less effect than noise on
the AM drive line AB1/2 PLAD pin 5 (white wire). Check this for any fluctuations
and retrace these to A2/2 board if necessary.
(3) FM noise. Check to establish first that the fault is common to carrier
frequency selections of both above and below 62.5 MHz or confined to one range
only. Ensure that the measuring instrument is not at fault.
Below 62.5 MHz only. Here the 160 MHz loop is suspect. If the frequency of the
disturbance is comparatively high (above several hundred hertz), check AB1/2,
160 MHz VCO circuit particularly around TR1. Scintillation in the capacitors can
cause an audio crackling noise. This can be checked by monitoring the 2305 LF
output with a loudspeaker.
Above and below 62.5 MHz. With noise in this category it will be necessary to
| determine whether oscillators or the control signal is at fault. Selecting carrier
ee frequencies of 352 and 354 MHz respectively will change from one oscillator to the
other. This will indicate a fault on one or the other oscillator unit if either of these
are faulty. Use of the MOD ON-OFF selection will switch AA1/1 phase modulator
on and off. If the FM is set to 0 Hz, this is the next most likely cause. Also check
AA1/1 PLT pin 10 (black wire) LF FM line. To check the performance of the
modulator signal path select EXT MOD and a deviation of 99.9 kHz. If the noise
increases use Second function 3 to control the gain of A2/2 IC20, (address 09 and
10), A2/2 IC11 (address 04) and A2/2 IC19 (address 07 and 08) until the noise level
drops. The cause should then be apparent.
Note ...
Other inadequately screened instruments radiating magnetic fields at the line fre-
quency can also be the cause of excessive hum components. If noise is present on
both oscillators with the FM modulation off and there is no apparent noise on the
EM line A2/2 PLM pin 12 (black wire) - look for 100 pV or less (in the 50 Hz -
50 kHz bandwidth), suspect the loop error amplifier if this is excessive. Check the
noise on the VCO TUNE A line at A2/2 SKM pin 16 (red wire); this should be
approximately 1 mV p-p. Measurement bandwidth is unimportant in this case.
_ 46881-891U
Oct. 88 5-63
FAULT LOCATION a
Excessive carrier harmonics
51. If the harmonics are found to be in excess of the specification suspect AB1/2 RF
processing board. Check the instrument and establish which carrier frequency range is
at fault then carry out the remedial action suggested below.
52. Carrier frequencies up to 62.5 MHz. The harmonic level for these frequencies are
determined by three factors :
(1) The performance of fixed filters made up of printed circuit inductors and
ceramic plate capacitors.
(2) The drive levels to the mixer that creates the BFO signal.
(3) The linearity of the BFO output amplifier. Of the three, (2) or (3) are most “5
likely to be the cause of the problem. : }
53. Basic operation of the mixer drive may be checked by measuring the voltages on the 7
two following test points :
ABi/2 ‘ALC DOUBLER’ (adjacent to IC12a), should be 4 V +0.25 V.
‘ALC LF’ (adjacent to R13) with a 50 Q load connected should be as follows :
6.5 V - 7.5 V at a level of -10 dBm and
6V -7.5 V ata level of 0 dBm.
Notes ... .
(1) When monitoring the ‘ALC DOUBLER’ voltage, some variation of voltage will be
observed across the frequency band. |
(2) Poor alignment of the LF AM MOD tuning capacitor C18 may also be a cause of a
voltage abnormality on the ‘ALC LF’ test point.
54. Fault finding on the two stage output amplifier should be simple with each stage | S
being independently biased. Rl 33 and R138,139 are present to prevent ultra high a
frequency oscillations which would otherwise give misleading results. Voltages
expected are +3.1 V at TR14 collector, and +6.5 V at TR17 collector. C160 may be
disconnected if required allowing for the injection of a test signal to be applied through
the amplifier.
55. Carrier frequencies from 62.5 MHz to 250 MHz. The factors that influence the
harmonic content for this frequency range are the following :
(1) Signal divider output balance
(2) Fixed LC filters
(3) Linearity of output amplifiers
Of the three (1) or (3) are the most likely cause of the problem. The second harmonic
performance for the half octaves 62.5 MHz — 88.25 MHz and 125 MHz - 1 76 MHz are
determined by the balancing of the Q and Q outputs of AB1/2, IC11. The signal quality
may be checked before reaching the output amplifier by connecting a 500 Q oscilloscope Sa
probe across C60.
46881-891U
564 ‘Oct. 88
FAULT LOCATION
56. A self biasing arrangement, designed to maintain maximum sensitivity of the
divider, should result in a voltage of approximately +3.6 V on AB1/2 IC11 pins 6 and 11.
The output amplifier levelling loop should be +11.5 V to +12.5 V at 0 dBm with a 50 Q
load connected. (Note that D42 and D43 are matched devices). A test signal can be
injected by disconnecting one side of C102 at the junction of R92. Apply the signal to
C102, via AC coupling and at a level of 0 dBm.
57. Carrier frequencies from 250 MHz - 500 MHz. This frequency range is derived
from the fundamental oscillators and uses a combination of a tracking notch filter and a
fixed low-pass filter. Generally the second harmonic that reaches the output amplifier is
low enough so that the amplifier distortion is what is actually seen at the output. The
notch provides cover for the half octave 250 - 353 MHz. Use is made of the same data
as that obtained for the band pass filter. To ensure correct tracking L13 (wire loop) is
mechanically adjusted to cancel the second harmonic at 250 MHz. If the output
amplifier is suspected carry out the checks given in the previous paragraph.
58. Carrier frequencies from 500 - 1010 MHz. This doubler range uses a voltage
tuned band-pass filter to reject unwanted components. No mechanical adjustment exists
for this filter; it relies on the approximate tracking of D34 - D37 varactor di
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